Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

Abstract: A system and method for controlling a converter of a power stage receiving an adapter current for providing current to a load. The converter is operative in a buck mode for charging a battery and in a boost mode for discharging the battery to the load to supplement adapter current. The adapter current is compared with a predetermined level to develop a control signal, and at least one pulse control signal is developed based on the control signal and used to control the modulator. The modulator operates the converter in the buck mode when the adapter current up to the predetermined level, and operates the converter in the boost mode when the adapter current exceeds the predetermined level. The battery current may also be monitored to adjust the control signal to limit battery charge or discharge current in both modes.

Abstract: A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.

Abstract: Generalized virtual inspectors are provided. One system includes two or more actual systems configured to perform one or more processes on specimen(s) while the specimen(s) are disposed within the actual systems. The system also includes one or more virtual systems coupled to the actual systems to thereby receive output generated by the actual systems and to send information to the actual systems. The virtual system(s) are configured to perform one or more functions using at least some of the output received from the actual systems. The virtual system(s) are not capable of having the specimen(s) disposed therein.

Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: Technologies pertaining to designing microsystems-enabled photovoltaic (MEPV) cells are described herein. A first restriction for a first parameter of an MEPV cell is received. Subsequently, a selection of a second parameter of the MEPV cell is received. Values for a plurality of parameters of the MEPV cell are computed such that the MEPV cell is optimized with respect to the second parameter, wherein the values for the plurality of parameters are computed based at least in part upon the restriction for the first parameter.

Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Abstract: A system and method of supplying 240 volt charging for an electric vehicle, while also allowing for 120 volt electrical devices to be used in the area, includes a charging station having a 240 volt input, a 240 volt electric vehicle charge plug electrically connected to the 240 volt input, a 240 volt to 120 volt step down transformer, a 240 volt side of the step down transformer electrically connected to the 240 volt input, and a 120 volt power outlet electrically connected to a 120 volt side of the step down transformer. The charging station is electrically connected to a 240 volt circuit that has been converted from a 120 volt circuit that has previously existed in the area.

Abstract: An apparatus for wireless charging using radio frequency (RF) energy includes a charger coil configured to produce RF charging energy as a magnetic field, the charger coil located proximate to a magnetic material and a metal material, the magnetic material and the metal material located to attenuate the magnetic field generated by the charger coil beyond a plane defined by a major surface of the magnetic material and the metal material, a first portion of the magnetic material underlying the charger coil and a second portion of magnetic material overlying the charger coil.

Abstract: An electronic design automation (EDA) tool that analyzes a circuit design to identify sequential elements (flip-flops) that do not need to be reset, for example, because they do not need to be initialized in order to be in a known state, and converts the identified sequential elements to non-resettable circuits, which saves power and area.

Abstract: A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.

Abstract: A battery pack having a contactless charging circuit (95) that rectifies power received by a receiving coil (1), and a battery pack control section (91) with a connection decision section. The battery pack control section (91) is configured to judge whether or not the battery pack is connected to the body of a battery powered device (101) based on the rectified voltage of the contactless charging circuit (95). This decision utilizes the fact that the charging circuit is in a no-load condition and the rectified voltage is high when the battery pack is not connected to the battery powered device, and allows reliable judgment of whether or not the battery pack (90) is attached to the battery powered device.

Abstract: Provided is a power supply device integrally combined with an electrical device body including a motor, comprising a rechargeable battery for supplying power to the motor, a microcomputer for detecting a residual capacity and a battery voltage of the battery, and a switching element provided between the battery and the microcomputer. The microcomputer stops charging the battery when the detected residual capacity has become 100%, and when the detected value of the battery voltage has become lower than a peak value after the value of the battery voltage passes the peak value, making it possible to prevent overcharging of the battery. The microcomputer also controls to turn off the switching element to stop the power supply from the battery to the microcomputer when the residual capacity becomes less than a predetermined threshold value, making it possible to reduce power consumption.

Abstract: A power system adapted for supplying power in a high temperature environment is disclosed. The power system includes a rechargeable energy storage that is operable in a temperature range of between about seventy degrees Celsius and about two hundred and fifty degrees Celsius coupled to a circuit for at least one of supplying power from the energy storage and charging the energy storage; wherein the energy storage is configured to store between about one one hundredth (0.01) of a joule and about one hundred megajoules of energy, and to provide peak power of between about one one hundredth (0.01) of a watt and about one hundred megawatts, for at least two charge-discharge cycles. Methods of use and fabrication are provided. Embodiments of additional features of the power supply are included.

Abstract: A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.

Abstract: Systems and methods for generating compact models that include the effects of physical and electrical variations independent of available hardware data. A method includes generating a physics-based model using a technology computer-aided design (TCAD) of the one or more devices in a technology node. The method further includes deriving electrical parameters for the one or more devices from the physics-based model. The method further includes generating the compact model based on the derived electrical parameters.

Abstract: A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.