Abstract: A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.

Abstract: A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

Abstract: A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number of routing tracks that may be connectable to that port. Routing priorities for the nets of the netlist may then be created using the port obscurity factors of the ports in the net. Routing may then be done in the order determined by the routing priority list and the generated layout information stored in a computer useable medium. In some cases, routing may be performed using multiple routing passes where a new routing priority list may be calculated for each routing pass.

Abstract: A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.

Abstract: A method of manufacture of a mask system includes: providing design data; generating a substantially circular optical proximity correction target from the design data; biasing a segment of the substantially circular optical proximity correction target; and generating mask data based on the shape produced by biasing the segment of the substantially circular optical proximity correction target.

Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.

Abstract: Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

Abstract: A circuit design assist system that receives a user instruction for registering an interface section of at least two circuits as a template, and generates a plurality of circuit patterns of the interface section, each pattern having a different combination of electrical properties of at least one device included in the interface section for evaluation. When an evaluation result indicates that the interface section operates normally for each of the circuit patterns, the circuit design assist system registers the interface section as the template.

Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract: A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.

Abstract: A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining the outline information, the boundary information, and the auxiliary line information, when a command for recording position information of points within each of the boundaries is input; obtaining position information of the points within each of the boundaries; setting corresponding height values as height limit of height restriction areas corresponding to the points within each of the boundaries.

Abstract: A process for shortest path routing in computer-aided designs (CAD) is performed using an incremental graph traversal technique. This technique searches the shortest path routing trees in a graph by path exploration limited only to an incremented search region thereby reducing run time complexity. Graph traversal begins in the incremented search region, and propagates successive changes thereafter.

Abstract: A method of calibrating a lithographic process model is provided. The method includes providing a test pattern that includes a plurality of shapes; transferring the test pattern onto a photo-mask forming a resist image of the test pattern using the photo-mask; collecting model calibration data from the resist image; and calibrating the lithographic process model using the model calibration data, wherein the plurality of shapes of the test pattern have at least a first shape and a second shape, and distances from an edge of the first shape to an edge of the second shape over a range thereof, when being measured parallel to each other, differ from each other.

Abstract: A computer-implemented method of globally placing a circuit design on a programmable integrated circuit (IC) includes dividing, by a placement system, the programmable IC into a grid comprising a plurality of cells, assigning each component of a selected component type of the circuit design to one of a plurality of control set groups according to a control set of the component, and calculating a force including a control set force that depends upon overlap of control sets within the plurality of cells. The method further can include applying the force to at least one selected component of the circuit design and assigning components of the circuit design to locations on the programmable IC by solving a set of linear equations that depend upon application of the force to the at least one selected component to create a global placement. The circuit design including the global placement can be output.

Abstract: A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.