Abstract: A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.

Abstract: A method for producing a gate turn-off thyristor (GTO) having a semi-conductor substrate (1) with at least one p-conducting anode layer (4), one n-type base layer (6), one p-type base layer (7) which is in electrical contact with a gate, and one n-conducting cathode layer (8) has a cathode layer (8) with a highly doped zone (10) acting as an n.sup.+ emitter and a lightly doped zone (9) in which highly doped zone (10) adjoins the surface of the semi-conductor substrate (1) and has a doping density which is at least an order of magnitude higher than that of the p-type base layer (7), the lightly doped zone (9) is situated between a pn junction J.sub.1, produced by the p-type base layer (7) and the cathode layer (8), and the highly doped zone (10) of the cathode layer (8) including producing the doping profile of the cathode layer in first and second diffusion steps, the depth and the breakdown properties of the pn junction J.sub.

Abstract: The conducting layer, such as polysilicon, which electrically connects spaced apart semiconductor islands of a semiconductor-on-insulator, such as sapphire, integrated circuit device is further spaced from the base, sides and upper edges of the islands (identified as sites for origination of undesirable leakage currents during operation) by an underlying insulating layer which may include silicon oxide with a dopant such as phosphorus or boron. During processing, the islands provide a self-masking effect when illumination is first passed through the sapphire substrate to expose photoresist. Refraction of the illumination around the upper edges of the islands provides a convenient way to form the insulating layer so that it lips over the edges and slightly onto the top of the islands.

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Abstract: A method of characterizing A.C. performance of an integrated circuit based upon D.C. measurements utilizing a process monitor circuit. The process monitor circuit provides a D.C. output having a magnitude which varies with the frequency of an oscillator section of the monitor circuit. The frequency is a function of both A.C. and D.C. performance, therefore the process monitor output signal is indicative of such performance. Since D.C. measurements may be made while the integrated circuits are in wafer form utilizing a conventional wafer prober and parametric tester, it is possible to detect A.C. performance problems very early in the manufacturing process.

Abstract: A technique for effectively doping a storage node capacitor plate constructed from low temperature deposited rugged polysilicon. A phosphorus silica glass is deposited prior polysilicon deposition and used primarily to uniformly diffuse n-type dopants into the subsequently deposited rugged poly capacitor plate. This doping technique eliminates the need for high temperature doping and will maintain the rugged surface in the poly of the capacitor plate.

Abstract: In making a power diode with high reverse voltage rating, corrosion of the silicon wafer surface by gettering substances is avoided by employing two different diffusion steps. In the first step, boron and phosphorus are respectively applied to opposing major surfaces of the disk-shaped semiconductor body (10) and driven into it by heating to a predetermined temperature. Gettering is employed to increase the charge carrier lifetime and thereby reduce the forward voltage drop of the diode. The gettering is carried out in a second diffusion step at a diffusion temperature sufficiently reduced with respect to the diffusion temperature of the first step to avoid significantly affecting the depth of diffusion of the doping substances into the semiconductor body.