Abstract: A semiconductor body (1 ) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means (6,7) are used to form over first and second areas (20 and 21) of the one major surface (2) windows (8,9,10) in the insulating layer (5) through which impurities are introduced to form a relatively highly doped region (11) of the opposite conductivity type adjacent the first area (20) and a relatively lowly doped region (12) of the opposite conductivity type adjacent the second area (21). The surface (5a) of the insulating layer (5) is exposed prior to introducing impurities of the one conductivity type for forming a region (13) within the relatively lowly doped region (12) of the opposite conductivity type and with a dose sufficient to form the region (13) but not sufficient to overdope the relatively highly doped region (11) so avoiding the need to mask the first area (20) during this step.

Abstract: In a semiconductor memory device having a floating gate structure, the floating gate electrode is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film, formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film is formed on the silicon substrate, portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer is formed on the silicon substrate by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film formed on the floating gate electrode can have a high breakdown voltage.

Abstract: The invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following, formation of a floating gate electrode on a region predetermined for the formation of the first conductive channel across an insulation film, followed by superimposition of a control gate electrode on the floating gate electrode across another insulation film. After completing the formation of the stacked gate electrode unit, the first conductive impurities are injected into silicon substrate by applying a minimum of 8 degrees of angle against the normal of this substrate under aid of ionic injection, and then forms a region containing strong density of the first conductive impurities adjacent to the boundary of a layer of diffused second conductive impurities which is at least predetermined to become the drain region of the transistor incorporating the stacked gate electrode unit.

Abstract: A method for manufacturing a semiconductor device wherein in the case where a Bi transistor and a CMOS transistor are to be formed on a first conductive semiconductor substrate, a gate oxide film on an active base in a Bi transistor formation region is partially removed by a predetermined pattern so as to form the opening of the gate oxide film, a polysilicon layer having second conductive impurities doped at a high density is patterned over the edge of the opening, and the emitter region of the Bi transistor is formed from the portion in which the active base comes into contact with the first conductive semiconductor substrate, i.e.

Abstract: A silicon on insulator structure and method of making the structure. A high purity, substantially defect free silicon wafer is the basis for forming a final thin silicon layer on an insulator layer, the silicon having substantially the same chemical and structural state as the starting silicon wafer. Dopant atoms of MeV energy range are implanted into the silicon wafer, the silicon wafer having an insulator layer coupled thereto; and an underlying silicon carrier wafer is coupled to the insulator. The implanted silicon wafer undergoes preferential etch stop removal of the silicon up to the implanted dopant layer, followed by selective removal of the dopant atom layer, leaving the desired high quality silicon layer on an insulator substrate.

Abstract: In a MOS transistor or memory cell that uses a thin oxide film as a gate insulation film, ion-implantation-induced damage protection films (mask oxide films) are formed on side walls of a polysilicon gate electrode to minimize flaws in the structure of the thin oxide film right under the polysilicon gate electrode edge, which are induced by the ion implantation performed during the process of forming self-aligned source and drain regions.

Abstract: An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.

Abstract: A semiconductor device is formed by a process in which a diffusant penetration layer and a diffusant source layer containing a boron dopant are formed overlaying the surface of a semiconductor substrate. The diffusant source layer is annealed to cause the boron dopant to controllably diffuse through the diffusant penetration layer to the semiconductor substrate to form a doped region at the surface. The diffusant source layer and the diffusant penetration layer are removed and a gate insulator is formed on the substrate surface overlaying the doped region. An N doped gate electrode is then formed overlaying the gate insulator.

Abstract: A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Abstract: A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.

Abstract: One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface and in the bottom of the trenches which extend from one end to the other of the memory array.

Abstract: A CCD imager cell (36, 38) is formed at a face of a semiconductor substrate (10) and has first (36) and second (38) phase regions. A first clocked well (14) is provided for receiving charge integrated in the first phase region (36). A second clocked well (16) is provided for receiving charge integrated in a second phase region (38) adjacent the first phase region (36). A first gate (20) is insulatively disposed over the first clocked well (14), and a second gate (22) is insulatively disposed over the second clocked well (16). A controller controls .phi..sub.1 and .phi..sub.2 pulses such that the charge is transferred from a selected one of the first and second clocked wells (14, 16) to the other, thus integrating all of the charge in the cell into one clocked well thereof. This unified charge is then transferred out from clocked well to clocked well.

Abstract: A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, selectively removing the insulating film to expose a surface of the semiconductor substrate, doping an impurity in the semiconductor substrate using the selectively formed insulating film as a mask, thereby forming an impurity region of one conductivity type, forming a photoresist film on the entire surface of the semiconductor substrate in an area including the insulating film used as the mask, selectively removing only the photoresist film on the insulating film to leave the photoresist film on only the impurity region of one conductivity type, removing the insulating film at a portion from which the photoresist film is removed, thereby exposing the surface of the semiconductor substrate, and doping an impurity using a remaining photoresist as a mask to form an impurity region of the other conductivity type in the exposed surface of the semiconductor substrate.

Abstract: Along the outline of a first doped region, a first mask is formed. The mask is made up of a dielectric opposed to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant in a second region which will only be defined along the outlines of the first region.

Abstract: A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.

Abstract: An antireflection coating (16) for use with a photolithographic process comprises a layer of organic material that planarizes the surface upon which a photoresist layer (21) is deposited, is highly absorptive of deep ultraviolet actinic light, and can be plasma etched along with an underlying metal layer (11), thereby obviating the need for a separate step to remove the exposed antireflection coating prior to metal etch.

Abstract: A method of manufacturing a semiconductor device comprising a semiconductor body (3) with a surface (10) on which capacitors (2) are provided, which form memory elements, with a lower electrode (11) including platinum, a ferroelectric dielectric material (12) and an upper electrode (13) is presented. In the method according to the invention, the electrodes (11, 13) including platinum are formed by the successive deposition on a surface of a first layer (19, 26) comprising a metal from the group titanium, zirconium, hafnium or an alloy of these metals, a second layer (20, 27) comprising platinum, and a third layer (21, 28) comprising a metal from the group titanium, zirconium, hafnium, or an alloy of these metals, upon which the semiconductor body is heated in an atmosphere containing oxygen. The first metal layer ensures a good adhesion of the electrode, the second layer acts as the electrode proper, while the third metal layer counteracts adverse effects of the first layer.

Abstract: A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

Abstract: The present invention provides a method of fabricating a virtual ground EPROM cell in a silicon substrate of P-type conductivity. In accordance with the method, a gate oxide layer is formed on the silicon substrate. This is followed by the formation of a first layer of polysilicon (poly 1). Next, a composite structure comprising oxide-nitride-oxide (ONO) is formed on the first polysilicon layer. Next, a photoresist mask is used to define parallel lines of ONO/poly 1. After etching the ONO/poly 1 to define the parallel lines, an arsenic implant is performed while keeping the photoresist mask in place to define N+ bit lines between the lines of ONO/poly 1. After the photoresist is stripped from the parallel lines of ONO/poly 1, an oxidation step is performed to complete the oxidation of the ONO and to simultaneously grow a differential oxide between the lines of ONO/poly 1.