Abstract: A method for introducing an impurity into a polysilicon formed on an insulating film is described. A silicate glass layer (13) containing As is formed on a polysilicon layer (12) formed on an insulating film (2) and is thermally treated to introduce As into the polysilicon layer (12). The silicate glass layer (13) has a concentration of arsenic of not less than 25 wt. %, calculated as As.sub.2 O.sub.3 and the thermal treatment is effected in an atmosphere of a mixed gas of N.sub.2 and O.sub.2 with an oxygen partial pressure ratio of 0.05-0.7 at not lower than 1000.degree. C. for not shorter than 60 minutes.

Abstract: An electrically, programmable read-only memory cell is formed at a face (10) of a semiconductor layer (12). This cell comprises a doped drain region (36) and a doped source region (38) that are spaced from each other by a gate region (40). An ONO memory stack (28) is formed to extend over a portion of the gate region (40) that adjoins the drain region (36). The memory stack (28) is substantially spaced from the source region (38). A select gate insulator layer (30) is formed over the remainder of the gate region (40), and is preferably of the same thickness as the memory stack (28). A suitable gate conductor (32) is then deposited over insulator layers (26, 30). By being substantially spaced from source region (38), the memory stack (28) of the invention avoids the formation of ONO hole traps.

Abstract: An N.sup.+ buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N.sup.+ buried layer can also be formed under N-channel input/output devices. The N.sup.+ buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.

Abstract: A method and apparatus for processing a fine pattern of a sample of one of an electronic device, molecular device and bioelement device, wherein a needle having a sharpened tip is disposed in opposed relation to the sample with a gap therebetween. A voltage is applied between the needle and the sample so as to enable a tunnel current and/or a field emission current to flow therebetween and the fine pattern is provided to correct the fine pattern by effecting at least one of removal, repositioning, annealing and film formation of at least one of individual atoms and individual molecules.

Abstract: A solid-state image sensing device has an overflow drain structure for purging superfluous charges. The overflow drain structure includes a gate electrode (34), channel regions (35), and a drain region (32) formed inside each groove (26) formed on a main surface of a semiconductor substrate (6). Optoelectro transducers (4) are formed on main surface regions of the semiconductor substrate continuous with each groove. The drain region is formed on side walls and a bottom wall of each groove by oblique ion implantation. The overflow drain structure formed inside the groove occupies a reduced area on the main surface of the semiconductor substrate and increases its opening ratio.

Abstract: Disclosed is a preferable method for producing an avalanche photo diode in which an impurity-doped region having a relatively high concentration and a step-like distribution has a step portion in another impurity-doped region having a relatively low concentration and a gradational distribution so that the circumferential portion of the high concentration region is made shallow in comparison with the central portion of the same, the step portion having a shape so that the radius of curvature thereof varies continuously.

Abstract: A semiconductor silicon wafer usable for integrated circuits has beveled portions unsymmetrically formed along circumferential edges of front and back surfaces thereof. An angle between an inclining surface of the beveled portion and a main surface on the back surface side is larger than that between the inclining surface of the beveled portion and the main surface on the front surface side. Therefore the circumferential edges are prevented from being chipped.

Abstract: A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

Abstract: A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system.A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.

Abstract: A method for fabricating floating gate memory arrays with improved electrical erase characteristics and a reduced gate oxide defect density is described. According to the invented method, a protective polysilicon layer is deposited immediately following growth of the tunnel or gate oxide. The polysilicon layer caps the gate oxide--protecting it from exposure to defect-causing contaminants and to insure that a uniform tunnel oxide thickness is maintained across the entire length of the channel; especially over the electron tunneling regions. Following application of the protective polysilicon layer, a second polysilicon layer is deposited and merges with the first polysilicon layer to form the floating gate for the device. Erase speed is improved for flash EEPROM devices fabricated according to the present invention by about 5-100 times.

Abstract: A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (<200 angstroms) silicon nitride layer. The top layer comprises a CVD oxide deposited in a thickness up to 150 angstroms. The capacitively measured effective thickness of the complete structure is about 200 .ANG. or less. The top layer CVD oxide has a thickness greater than the bottom oxide layer and greater than or equal to that of the silicon nitride layer and may also extend beyond the EPROM cell to form at least a part of the peripheral transistor dielectric.

Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. A high quality tunnel oxide is grown on the channel regions of the device, followed by deposition of a polysilicon buffer layer. The use of the polysilicon buffer layer results in short reoxidation beaks. The field oxide is grown in a short, low temperature wet oxidation step, enhanced by the presence of heavy dopant implants. The use of a short, low temperatue oxide growth allows the use of thin nitride masking members and results in short reoxidation beaks as well as less stress on the substrate during field oxide growth. Also, since a low temperature field oxidation is used, the quality of the tunnel oxide will be maintained. The thin nitride masking members are removed in a wet etch process which does not degrade the underlying polysilicon buffer layer.

Abstract: A semiconductor photodetector is disclosed which comprises a pn junction formed in a semiconductor substrate and a pair of electrodes for applying a reverse bias to the pn junction, in which at least a part of the junction plane of the pn junction has been metamorphosed by enhanced diffusion. Hence the pn junction from an outer peripheral portion and a central portion is made smooth.

Abstract: An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All but opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.

Abstract: The present invention relates to a semiconductor device e.g., a CMOS, comprising a denuded region and a bulk-defect region, as well as a process for producing, e.g., CMOS. In a conventional CMOS, the distance (dp) between the bulk-defect region and p.sup.+ -type source or drain region (dp) is greater than the distance (dn) between the bulk-defect region and the p well (dn). As a result, a leakage current can be generated in the PN junction. In order to eliminate the problems caused due to dp>dn, the present invention forms in a semiconductor substrate a bulk-defect region having a depth which is nonuniform in accordance with the nonuniform depth of the semiconductor elements.

Abstract: A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Abstract: A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide/nitride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel.

Abstract: This invention comprises a Pd layer formed on an n-type GaAs semiconductor crystals, and a Ge layer being formed on the Pd layer, characterized in that the thickness of the Pd layer is between 300 .ANG. and 1500 .ANG. and the thickness of the Ge layer is between 500 .ANG. and 1500 .ANG..In addition, this invention provides an ohmic electrode forming process for compound semiconductor crystals for forming an ohmic electrode on an n-type GaAs semiconductor crystal, comprising a first layer forming step for forming a palladium (pd) layer on a compound semiconductor crystal; a second layer forming step for forming a germanium layer (Ge) on the Pd layer; and an annealing step for annealing the Pd layer and the Ge layer by a rapid thermal annealing treatment.The Pd layer is formed between 300 .ANG. and 1500 .ANG. in the first layer forming step; the Ge layer is between 500 .ANG. and 1500 .ANG.