Abstract: A method for producing a box type quantum well structure includes generating ion clusters, linearly accelerating the clusters with an electric field, passing the accelerated cluster ions through a further field perpendicular to the accelerating direction, causing the cluster ions to follow different ion orbits in accordance with the number of constituent atoms of the respective cluster ions, intercepting the cluster ions having a predetermined number of atoms with a substrate arranged in the orbit of the cluster ions having a predetermined number of atoms. A neutral particle shielding plate is provided along a straight line between the substrate and the cluster ion source to prevent neutral particles from flowing toward the substrate. Thereby, GaAs boxes having the same size can be obtained and variations in the quantum effects of the boxes can be reduced.

Abstract: A method and article of manufacture are disclosed comprising substantially increasing the electrical activation and mobility of electrons in a III-V semiconductor material containing minor amounts of oxygen by doping a III-V crystalline material with an n-type dopant and adding or implanting an oxygen reactive element in the III-V material where the doses of dopant and implanted oxygen reactive element are low enough to effect this increase. These doses typically do not exceed about 1E13 cm.sup.-2 and 4.5E12 cm.sup.-2 respecitvely. The added or implanted oxygen reactive element preferably is at a dose less than the n-type dopant. Experimental data indicate that the added or implanted oxygen reactive element acts as a gettering agent to form an oxygen depleted zone between dopant and oxygen reactive element regions.

Abstract: A method is disclosed for the incorporation of relatively high vapor pressure elements into good quality GaAs at extremely low T.sub.s using the migration enhanced epitaxy techinque. Zinc was doped in GaAs material grown at a low T.sub.s of 120.degree. C. Zinc may thus be used as a p-type dopant replacing more toxic Be. Similarly, other high vapor pressure elements can be incorporated much more efficiently into the material grown at low T.sub.s.

Abstract: A method for diffusing n type impurities from a solid phase source into a III-V compound semiconductor includes depositing an amorphous or polycrystalline selenium or sulfur film on the III-V compound semiconductor and diffusing selenium or sulfur from the film into the compound semiconductor by annealing. Highly controllable diffusion of n type impurities in a high concentration is achieved.

Abstract: A method for manufacturing a static induction type semiconductor device is to form gate zones on a surface side of a semiconductor substrate, to cover the surface including the gate zones with an oxide film, to form through the oxide film apertures for providing cathode zones in the substrate, the apertures respectively overlapping partly each gate zone, and to form the cathode zones with thermal diffusion of an impurity carried out through the apertures, the cathode zones thus partly overlapping the gate zones. Concentration of the impurity as well as the depth of the diffusion at thus made impurity diffusion zones can be thereby stabilized, and eventually electric characteristics of enhancement type, static induction type semiconductor device can be sufficiently made stable.

Abstract: A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Abstract: In fabricating a semiconductor device, when impurities are diffused from a silicon oxide layer containing the impurities to a semiconductor layer, a diffusion atmosphere is controlled so as to oxidize or reduce a specified impurity to thereby control the diffusion coefficient of the impurities in the silicon oxide layer. Thus, it is possible to form a diffusion layer having a desired impurity profile under a good control.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

Abstract: A method of diffusing boron into semiconductor wafers is disclosed which essentially includes boron deposition and boron diffusion. The deposition is performed from 900.degree. to 1,000.degree. C. and the diffusion at a temperature of 890.degree. to 1000.degree. C. Oxidation induced stacking faults are greatly reduced.

Abstract: Methods of forming a semiconductor substrate and a device oriented substantially along a crystal direction other than a crystal direction that falls along a cleavage plane and the substrate and device formed by each method are disclosed. An ingot of monocrystalline material is formed and marked to denote a crystal direction other than a crystal direction that falls along a cleavage plane. The ingot is lapped to form a semiconductor substrate having a mark denoting a crystal direction other than a crystal direction that falls along a cleavage plane. A device is formed on the semiconductor substrate having a monocrystalline layer, such that a field oxide-active area edge or a gate electrode lies substantially along a crystal direction other than a crystal direction that falls along a cleavage plane. The present invention may be used on any device where dislocation defects, a lateral diffusion, or a lateral oxidation is to be minimized.

Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Schottky diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Schottky diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Schottky diode (22). The base (54) of the trigger transistor (24) is biased during normal operations with a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: A method of reducing the leakage current of a III-V compound semiconductor device (10) includes providing the device with a confinement layer having two sections (13, 14). A first section (14) has a higher doping concentration than a second section (13). An energy barrier that confines minority carriers to an active layer (12) of the device (10) is formed by diffusing a dopant into a portion of the active layer (12) and the two sections (13, 14) of the confinement layer. During the diffusion, the conductivity type of a portion of the lower doped second section (13) is inverted while the higher doped first section (14) is not inverted.

Abstract: A method for producing a semiconductor device on a semiconductor layer provided on an insulator layer comprises the steps of providing an opening on the semiconductor layer to expose a top surface of the insulator layer, depositing a first material layer that has a hardness exceeding the hardness of the semiconductor layer on the semiconductor layer including the exposed top surface, and patterning the first material layer such that a patterned region of the first inorganic material is left in the opening with a gap separating the patterned region from the side wall of the semiconductor layer.

Abstract: The present invention relates to a semiconductor device which has not only high performance memory and logic by forming the low voltage and high voltage BiCMOS transistors in the same single semiconductor substrate, but also various functions and driving voltages by increasing the output power and noise margin, wherein the miniaturization of electronic products can be achieved by forming the low and high voltage BiCMOS transistors with various functions and also can achieve the high speed operation since a signal processing speed becomes fast.

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window are near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio.

Abstract: In making trench type semiconductor CCD by using oblique ion-injections into an oblong trench groove in a semiconductor substrate region for injecting impurity atoms, an injection angle .alpha. for injecting a first conductivity type impurity to form isolation region into the side walls and also for injecting a second conductivity type impurity to form a charge transfer region thereon is selected less than .pi./4, and another injection angle .beta. for injecting the same impurity into the end wall to form the end part of the isolation region and a third injection angle .gamma.

Abstract: A method for producing a photodetector device includes depositing a plurality of spaced apart light absorption regions at intervals on a substrate, depositing an insulating layer on the substrate and covering the light absorption regions, producing a first conductivity type semiconductor layer on the insulating layer, and producing second conductivity type semiconductor regions by selectively diffusing impurities into regions of the first conductivity type semiconductor layer until the impurities reach the insulating layer.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.