Abstract: A method for producing a photoelectric converting device having an electrode formed across an insulating layer on a control electrode region. The control electrode region and main electrode region are formed by a self-alignment process utilizing a field insulating layer as a mask. The insulating layer is formed on the control electrode region with the electrode formed thereon.

Abstract: An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polycrystalline silicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

Abstract: A process for fabricating ultra-high density (e.g., 64Mbit) contactless EPROMs and/or flash EPROMs in a silicon substrate is described. Spaced-apart island members are formed of poly 2/ dielectric/poly 1 layers over gate oxide regions. Each island member is associated with one of the cells within the array, and is separated from each other by trenches extending down to either the field oxide or substrate regions. Elongated, parallel, spaced-apart source/drain regions are formed on adjacent sides of the channel regions by ion implantation. The trenches are then filled with an insulating material and a plurality of wordlines patterned across the array. Each wordline makes electrical contact to the control gate members associated with the single row of cells within the array.

Abstract: A solid state image sensing device comprises photoelectric converting portions (8) and charge coupled portions. A plurality of parallel trenches (2) are formed on a main surface of a semiconductor substrate (1). Photoelectric converting portions are on the surfaces of the semiconductor substrate on both sides of each of the trenches. Charge transfer portions corresponding to the photoelectric converting portions are independently formed on the side surfaces of the trenches. Insulating and isolating regions (15, 29, 30) are formed on the bottom portions of the trenches. By providing two independent charge transfer portions in one trench, the area occupied by the charge transfer portions can be reduced.

Abstract: A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the resistance of the diffused region is changed in a known and predictable fashion and may be measured electrically, giving indirect but accurate evidence of contact size in a completely nondestructive fashion. The measurements may be made on completed devices. Method and structure are disclosed.

Abstract: A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects.

Abstract: A process for fabricating an integrated memory matrix of EPROM cells having a "tablecloth" organization, with source and drain lines parallel among each other and running between parallel strips of isolating field oxide, floating gate structures formed between said source and drain lines and control gate lines running parallel among each other and perpendicularly to said source and drain lines and over said floating gate structures, utilizes a mask through which a stack, formed by a second level polysilicon layer, an interpoly isolating dielectric layer, a first level polysilicon layer and a gate oxide layer, is etched for defining in a longitudinal sense the gate structures (i.e. the channel length) of the EPROM cells. The gate structures are subsequently defined in a transversal sense by etching through another mask a stack comprising a third level polysilicon layer deposited directly over said second level polysilicon layer, said interpoly dielectric layer and said first level polysilicon layer.

Abstract: An electrically-erasable, programmable ROM cell, or an EEPROM cell, is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small tunnel window, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. The bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ration of control gate to floating gate capacitance. Programming and erasure are provided by the tunnel window area, which is located near or above the channel side of the source. The window has a thinner dielectric than the remainder of the floating gate, to allow Fowler-Nordheim tunneling. By using dedicated drain or ground lines, rather than a virtual-ground layout, and by using thick oxide for isolation between bitlines, the floating gate can extend onto adjacent bitlines and isolation area, resulting in a favorable coupling ratio.

Abstract: A method for electrically connecting a bit line to a source electrode of the MOSFETs in a semiconductor device is disclosed and which comprises arranging a gate electrode mask to form gate electrodes which are spaced apart and formed on respective gate oxide layers such that a contact mask which when positioned within the space between the gate electrodes provides a gap, for mask misalignment and critical dimension loss during the contact mask patterning process, of less than about 0.3 micrometer, separating each gate electrode from the respective proximate side of the contact mask. A contact hole having a side wall is formed to expose the source electrode by utilizing the contact mask and etching a portion of the etch stop layer and a portion of the insulating layer above the source electrode by the contact mask patterning process. A second insulating layer is deposited over the entire surface of the device.

Abstract: The disclosure relates to a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps of providing a sample of a group II-VI compound, providing an enclosed ampoule having the sample at one end portion thereof and a group II element of the compound at an end portion remote from the one end portion, heating the sample to a temperature in the range of 350 to the melting temperature of the compound for about one hour while maintaining the group II element at a temperature more than 200.degree. C. below the sample temperature, heating the group II element to a temperature from about 5.degree. to about 50.degree. C. below the temperature of the sample while maintaining the sample at a temperature in the range of 350.degree. to 650.degree. C. both of about 15 minutes to about 4 hours, and then stoichiometrically annealing the sample at a temperature below 325.degree. C.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: A method of manufacturing integrated circuits includes steps: forming a first layer of polycrystalline silicon on areas of a semiconductor substrate previously covered with a dielectric material; forming a first insulating layer and a second thin layer of polycrystalline silicon acting as a shield; removing the second layer of polycrystalline silicon and the first insulating layer except from predetermined areas for containing a first type of electronic component; doping the exposed portion of the first layer of polycrystalline silicon; forming, by deposition, masking and removal, of a second insulating layer on the first layer of polycrystalline silicon in an area for containing a second type of electronic component; forming of a third layer of polycrystalline silicon; masking predetermined zones of this latter layer lying at least partially above the areas intended for the two types of electronic components, and removing the polycrystalline silicon external to these predetermined zones.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown without the use of a sacrificial-oxide growth and removal method. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase regon is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: According to the present invention, the incomplete silicon exposure is prevented by the sufficient overetching after the formation of an etching-stop layer on an oxide layer for protecting a conductive layer from the damage of the protective oxide layer when the self-aligned contact window is formed. Therefore, the thickness of the protective oxide layer can be minimized, and the bend of the chip can be improved whereby the following process will be accomplished easily.

Abstract: A dopant film contains an organic binder, an inorganic binder and a compound of an impurity element for diffusion. Both surfaces of the dopant film are coated with adhesive. Releasable sheets sandwich the dopant film. The dopant film permits automated alternate stacking with semiconductor wafers, providing an advantage of labor saving. When the alternate stacking is automated, it will become hard for the wafer breakage to occur, sharply decreasing the rate of breakage. Furthermore, since the adhesion of a semiconductor wafer improves, the variation in the diffusion depth will decrease. The semiconductor wafer manufacturing method includes the steps of impurity diffusion into both surfaces, dividing the wafer into two wafers in the direction of thickness, and polishing to a mirror surface each divided wafer opposite to the surface on which the impurity diffusion layer is formed. The material loss per wafer is reduced more than the conventional method due to the slicing into two wafers.

Abstract: A nonvolatile semiconductor memory device is provided including a doped semiconductor substrate and three gate conductor layers electrically insulated from each other in the cell area on the substrate. A first floating gate conductor layer is formed on the substrate and covered by a second control gate conductor layer, forming a twofold polycrystalline silicon structure. A third select gate conductor layer is formed along one side wall of the twofold structure of the floating gate and control gate conductor layers, having a side wall spacer structure. The first conductor layer serves as a floating gate; the second conductor layer serves as a control gate; and the third conductor layer serves as a select gate. A field oxide layer is provided to separate cells from each other. The control and the select gates are connected in a region between cells through the field oxide layer. By providing the third conductor in the form of a side wall spacer, the cell area can be greatly reduced.

Abstract: On a semiconductor substrate, a thin insulating film to be used as a gate insulating film, a thin polysilicon film and a thick mask layer are formed in the order and an opening for gate electrode formation is formed in the mask layer. After an ion implantation of impurities having the same conductivity type as that of the substrate is performed thereto through the opening to form, in the substrate, an impurity region having the same conductivity type as and impurity density larger than that of the substrate, the opening is filled with electrically conductive material. Thereafter, the mask layer is removed and an exposed first polysilicon film is removed to form a gate electrode comprising the conductive material and an underlying portion of the polysilicon film. Then, source region and drain region are formed in self-aligned manner with respect to the gate electrode.

Abstract: Electrical connection to a device region (3,4) of a semiconductor device is formed by providing a semiconductor body (1) having adjacent one major surface (12) a device region (3,4) bounded by an insulating region (19a,19b,9), providing an activating layer (11) on the one major surface (12), applying a flowable material as a layer (13) of photosensitive resist, exposing and developing the resist to define an opening (14) over a contact area (12a) of the device region (3,4), and selectively plating electrically conductive material into the opening (14) to form a conductive pillar (15) in electrical contact with the contatct area (12a). The layer (13) of photosensitive resist is removed after formation of the conductive pillar (15) and a layer of insulating material is then provided to cover the conductive pillar (15) and the surface (12). The insulating layer is then etched to expose a top surface (15a) of the conductive pillar (15).

Abstract: The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.

Abstract: According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).