Abstract: A novel method of making articles that comprise a periodic heteroepitaxial semiconductor structure is disclosed. The method pertains to growth of the periodic structure by MBE, CVD or similar growth techniques, and involves periodically changing the substrate temperature. For instance, a periodic multilayer GaAs/AlGaAs is grown by MBE, with the substrate temperature cycled between 600.degree. C. and 700.degree. C. The novel method can produce multilayer structures of uniformly high material quality.

Abstract: A metal film and a doped a-Si film are deposited on a glass substrate, and successively etched by photolithography using the same resist pattern, to form a metal electrode and doped a-Si layers. The doped a-Si layers thus formed are then re-etched to remove portions protruding from the metal electrode. Then, a non-doped a-Si layer and a transparent electrode are successively formed on the doped a-Si layer. A protection film may additionally be deposited on the glass substrate before the deposition of the metal film.

Abstract: An improved process is provided for fabricating short channel complementary metal oxide semiconductor devices. The devices comprise source and drain regions separated by gate regions. The process comprises forming a shallow channel doping region (12') beneath the surface of a semiconductor (10) and forming source-drain regions (20') of opposite conductivity type (formerly known as lightly doped drain structures) on either side of the shallow doping region. A gate oxide (16) is formed on the surface of the semiconductor above the shallow channel doping region and a gate electrode (18) is formed to the gate oxide prior to the formation of the shallow channel doping region. The process permits spacing of the channel doping from the source-drain doping with self-alignment. Further, the doping of the source-drain regions is not constrained to the values of the lightly-doped structures of the prior art.

Abstract: About 6 to 20 micrometer resistivity N- (600 ohm-cm and above) silicon is epitaxially deposited on N+ (0.01 to 0.1 ohm-cm) substrates. The resistivity of the epitaxial layer is lowered to 5 to 60 ohm-cm using neutron activated doping. A 1 micrometer p-well process is utilized to build natural (unadjusted) PMOS transistors in the bulk silicon. These transistors operate in the subthreshold region where the threshold or turn on voltages have to match closely across a large device. N-channel transistors are fabricated in a P-well. The advantage of using neutron activated doped silicon is that the carrier concentration is very uniform and therefore threshold variations are much smaller than in transistors built in conventional doped silicon. The use of a neutron doped epitaxial layer on a P-well CMOS process provides a novel approach to control dopant uniformity and thus uniform transistor characteristics as well as providing a heavily doped conventional substrate to enhance resistance to CMOS latch-up.

Abstract: A method of manufacturing a floating gate type nonvolatile memory cell having an offset region, wherein the length of the offset region is defined by the portion of the substrate covered by the injection blocking film formed on the side wall of the floating gate electrode. Thus, the offset region is self-aligned with respect to the side wall of the floating gate electrode. Moreover, since the insulating film formed on the floating gate electrode includes a nitride film, it is damaged little while the injection blocking film is being formed on or removed from the side wall of the floating gate electrode. In addition, when an oxide film is formed on the offset region, substantially no additional oxide film is formed on the nitride film in the insulating film on the floating gate electrode, and the thickness of the insulating film does not change.

Abstract: A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.

Abstract: The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.

Abstract: A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.

Abstract: A method of manufacturing a semiconductor acceleration includes oxidizing a silicon wafer, removing the oxide film and underlying silicon in a U-shaped pattern at a front surface of the wafer by etching to form a portion that is to become a cantilever, depositing a thin metal film covering the U-shaped pattern that is to become the cantilever, etching a recessed portion in the rear surface of the silicon wafer encompassing the U-shaped pattern, thereby forming the cantilever, dicing the silicon wafer into chips, and removing at least part of the thin metal film, thereby releasing the cantilever.

Abstract: A process for producing a CCD image sensor comprising the steps of: providing a light-receiving photo-diode region and a VCCD transmission region by injecting ions into a substrate at a predetermined distance, the injected ions being different in type from the substrate, covering the surface of the substrate with a gate oxide layer and a gate polysilicon layer, the gate polysilicon layer being deposited over the gate oxide layer, then removing the gate polysilicon layer only from the region over the light-receiving region, depositing a refractory metal layer over the whole etched surface by vacuum evaporation and then annealing the refractory metal into a silicide in the region thereof which is in contact with the gate polysilicon and removing the refractory metal from the unconverted portion of the refractory metal layer which overlies the gate oxide layer.

Abstract: The present invention is directed to a semiconductor memory device and a method for fabricating a semiconductor memory device, in particular a E.sup.2 PROM, having an improved tunnel area wherein electrons travel to and from a floating gate. The tunnel area is characterized by properties which lend to a relatively large number of programming and erasure cycles over the life of the E.sup.2 PROM. The tunnel area includes a tunneling gate which is fabricated via two implant stages. Because these two stages are separate from one another, each of the implant stages can be independently optimized to improve the properties of the tunnel area. Further, the windows used to define the implant regions are easily fabricated and are designed to facilitate formation of the implant regions. The method of defining the window lends to easy scaling of the process for advancing generations of technology.

Abstract: This invention relates to a method of manufacturing an Arsenic-including compound semiconductor device comprising the steps of forming an ion implantation layer in a specified region of an As compound semiconductor wafer, forming an As layer on the surface of the wafer, and annealing the water. In this manner, As evaporation in the ion implantation layer by annealing heat may be prevented. Accordingly, sufficient substitution of the implanted ions and the ions other than As ions composing the As compound may be achieved, thereby preventing lowering of the electrical activation of the As compound semiconductor device. In addition, the electrical activation becomes uniform over the whole area of the water.

Abstract: A method for making a device and the device itself which utilizes selectively doping part of the channel directly adjacent to the source to improve source-channel junction breakdown voltage is disclosed. This is accomplished through reduced dopant incorporation in the channel directly adjacent to the source during the channel doping steps. The portion of the channel which receives less channel dopant should not be so great that the charging of the floating gate is significantly altered.

Abstract: In interconnecting signal wires between circuit elements of a semiconductor integrated circuit chip having a multilayered wiring structure, the signal wires are divided or classified into a first group of signal wires with lower modification-requisite possibilty and a second group of signal wires with higher modification-requisite possibility. The first group of signal wires are allocated to a lower wiring layer and wired therein. Then, the second group of signal wires are allocated to an upper wiring layer and wired therein. The second group of signal wires are allocated to and connected in the upper wiring layer, so that a laser is allowed to be fired directly to the upper wiring layer for disconnecting the signal wire or a laser CVD is allowed to be easily implemented on the upper wiring layer for connecting the signal wire, thereby enhancing reliability of modification. The first group of signal wires not to be modified are allocated to and connected in the lower wiring layer.

Abstract: A memory cell is disclosed which comprises a filament channel transistor and a ferroelectric capacitor formed on a surface of a semiconductor substrate. The transistor comprises a substantially cylindrical channel filament which is formed substantially perpendicular to the substrate surface between the surface and the capacitor. The capacitor comprises a storage layer which can be formed of a ferroelectric material such that the memory cell is nonvolatile. The storage layer may also comprise a high dielectric material such that the memory cell is operable as a dynamic random access memory cell.

Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.

Abstract: In a semiconductor integrated circuit device having at least three conductor layers, a connection hole for the lower conductor layer and the upper conductor layer can be formed in self-alignment to the intermediate conductor layer after flattening the underlying insulation film for the upper conductor layer and deterioration of the insulation withstand voltage between the upper conductor layer and the intermediate conductor layer can be prevented.

Abstract: A simplified process of making an insulated gate transistor entails forming the active regions in a single diffusion step. The method includes the steps of implanting and diffusing impurities of a first conductivity type (p for n-channel devices), implanting and diffusing a heavy dose of impurities of the same conductivity type (p+ for n-channel devices), and implanting and diffusing impurities of the other conductivity type (n+ for n-channel devices), wherein the three types of impurities are diffused at the same time in the same step. In a preferred embodiment of an n-channel process, the p-type dopant is boron and the n-type is arsenic.

Abstract: A method is provided for correlating ion implantation from a silicon wafer (13) to a gallium arsenide wafer. A first dose of a predetermined amount of silicon ions is implanted into a silicon wafer (13). The first dose of the implanted silicon ions in the silicon wafer (13) is evaluated by a measuring system (10) that monitors a modulated reflected signal from the silicon wafer (13) and quantifies the signal as to the number of implanted silicon ions in the silicon wafer. If the measured quantity of implanted silicon ions is a desired amount of implanted silicon ions the same number of silicon ions is then implanted into the gallium arsenide wafer.

Abstract: The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent boron out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.