Abstract: A speech digitization system including novel encoder and decoder circuits that minimizes the number of resolution bits required to produce a given level of speech quality by optimizing the information content of the digital output signal from the encoder. This is accomplished by providing a companded speech digitization system that includes an amplitude function generator which is adapted to produce an amplitude function signal that maintains substantial duty cycles on the digital output signal over the entire audio amplitude range. Included in the novel amplitude function generator is a unique bias network that serves to center the duty cycle swing of the digital output signal from the encoder around 50% where the information content of the signal is statistically maximized.

Abstract: An analog to digital conversion method and apparatus includes the use of a scaling circuit 15 to scale the magnitude of an analog signal D applied to ADC 4 to within an acceptable input range. A calibration circuit 16 generates a signal M indicative of the effect of the scaling circuit 15 upon a digital signal E produced by the ADC 4. An adder 14 adds the calibration signal M and the digital signal E of ADC 4 to yield a digital output signal N which is the digital representation of measured analog input signal A.

Abstract: A method for coding binary data to be transmitted and a device for decoding coded data dispense with the need to transmit a direct-current component and make it possible to reconstitute clock signals from coded data without any addition of a particular channel. With this objective, the input signal constituted by a sequence of groups of eight binary data is converted to a coded signal constituted by a sequence of words of sixteen binary data associated respectively with the groups and having a data repetition frequency which is double the repetition frequency of the input signal data. The words are also chosen so as to ensure that each datum of the coded signal is followed or preceded by a datum having the same logic state. Furthermore, a sequence of particular words is inserted at the beginning of the message in order to permit easy recovery of clock signals at the time of decoding.

Abstract: A method and apparatus are provided for encoding an n-bit information word into an m-bit code word, n.gtoreq.2 and m>n, wherein the DC component of successive code words is minimized. The digital sum variation (DSV) of a plurality of preceding m-bit code words is used to determine which of, for example, two m-bit code words should be generated to represent the n-bit information word to be encoded. The m-bit code word whose disparity, when combined with the digital sum variation, reduces the digital sum variation towards zero is selected.

Abstract: An image signal processing system for converting an analog image signal into a digital or binary image signal, capable of representing half-tone or gray scale when the corresponding visual image is reproduced by a dot-matrix type printer, is provided. The present system includes storing means for storing at least an array of thresholds, at least one of the thresholds being different in level from the other to form an array pattern. Such a threshold array is used as a reference level in producing a binary image signal. Half-tone is represented by the degree of black dot density per unit area.

Abstract: A sampled data generation circuit includes a voltage controlled oscillator for producing an output signal with a frequency variable according to a control voltage, a sample and hold circuit for sampling and holding an analog input signal in response to the output signal from the voltage controlled oscillator, and a control circuit for detecting the difference between two successive sampled data generated from the sample and hold circuit and supplying the voltage controlled oscillator with an output signal corresponding to the difference as the control voltage, thereby controlling the voltage controlled oscillator so that the greater the difference, the higher the frequency of the output signal from the voltage controlled oscillator is.

Abstract: A process and system are provided for transmitting additional information, called order track, superimposed on the information to be transmitted, by alteration of the coding law. The process involves:detection of at least one possible value of the information to be transmitted, for which the coding law is altered depending on the order track information.The first coding is transformed into a second coding by choice of one of several alphabets capable of ensuring such a transformation, this choice being effected depending on the value of the current numerical sum, in accordance with the coding law such that the value of this numerical sum is minimized.the output at one end of the transmission channel of the information is expressed in the second coding as altered by the order track.The information received at the other end of the transmission channel is transformed into information expressed in the first coding.The order track is detected by detection of the alteration in the coding law.

Abstract: In a digital-to-analog converter for bipolar signals all the bits change when the signals pass through the zero level. This results in a poor signal-to-noise ratio owing the small signal and the large noise contribution by the switching transients. The invention proposes to add a digital number to or subtract it from the digital input signal as an offset. As a result of this, the switching point is shifted towards a higher amplitude, which improves the signal-to-noise ratio and the distortion in the case of digital audio signals.

Abstract: An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 2 bits of unconstrained into 3 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. The encoder requires a lookahead of one future input vector (2 bits) and a look back at the last channel bit generated during the immediately preceding encoding operation. The error propagation due to a random error is, at most, 4 bits in bursts of 5. The hardware implementation is extremely simple and can operate at very high data speeds.

Abstract: A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.

Abstract: An encoder (100) for processing an input signal to produce a ternary coded data stream having supressed DC comprises circuitry, and its associated methodology, including an arrangement (120,130,150) for augmenting the data stream with a compensating set of code symbols as determined by the number of positive and negative code symbols in the data stream as well as all prior compensating code symbols. A decoder (200) processes the received signal to extract the symbols in the data stream corresponding to the input signal. In order to achieve a preselected end-to-end transmission rate with the encoder-decoder combination, the rate of the signal propagated between encoder and decoder is increased to compensate for the appended code symbols.

Abstract: An improved circuit for encoding data to be stored according to a 2,7 run-length limited code is disclosed, which features substantial simplification compared with prior art circuitry. The simplified circuit uses half as many memory elements as the prior art circuit and employs Boolean identities to simplify the logic elements encoding the data. In a preferred embodiment, the circuit is implemented using emitter-coupled logic. If necessary, the capacitance required by resistor-capacitor networks used to eliminate race conditions may be formed between a planar conductor on one side of a circuit board on which the circuit is laid out and a circuit element on the other.

Abstract: An analog signal representing the measured output of a condition responsive transducer is supplied to a dual slope integrating analog-to-digital converter also receiving a regulated constant reference signal. Using the integrator in a non-inverting mode, the A/D converter operates in a single conversion cycle by first positively integrating a value of analog signal below a maximum negative input voltage for a fixed time period and then negatively integrating a voltage signal corresponding to the differential between the reference voltage signal and the maximum voltage for a variable time period to a comparative threshold. During integration, digital counts proportional to the variable integration period are accumulated and emitted for operating a digital device such as a digital display.Digital linearization of the converter output can optionally be provided by use of a programmed microcomputer reading a programmable-read-only-memory (PROM) to run a variable frequency clock.

Abstract: A weighted current digital to analog converter (DAC) translates digital bits to corresponding analog signals by a suitably operated transfer circuit of (1) multiple parallel current sources for more significant bits and (2) binary weighted current sources for lesser significant bits. The number of resistors and the ratio of adjacent resistors is reduced in the transfer circuit relative to a ladder type DAC. Power saving and linearity are improved by the reduced number and ratio of adjacent resistors. The transfer circuit facilitates fabrication of the DAC in a semiconductor. Temperature stability is improved by proper location of the current sources in the semiconductor.

Abstract: The present invention relates to a decoder (10) for convolutional self-orthogonal codes which includes a multistage syndrome register (16) and is responsive to two separate threshold levels. The first threshold level, as in prior art arrangements, includes a first majority logic circuit (24) connected to selected stages of the syndrome register and functions to correct the information bits (X.sub.1 -X.sub.7) currently being processed. Instead of also using this majority logic circuit to correct the syndrome register, as in the prior art, the present invention includes a second majority logic circuit (28), which operates at a different threshold level than the first and functions to correct the selected stages of the multistage syndrome register.

Abstract: An analog-to-digital converter (ADC) uses pipe-lined data flow through parallelled charge transfer channels in a CCD for implementing a successive-approximation conversion algorithm. Successive charge splitting divides a standard level charge packet into binary-weighted charge packets, selectively added to develop the successive approximations against which charge packets dependent on analog input signal are differentially compared. These comparisons are made using floating gate sensors and auto-zeroed sense amplifiers. A battery of progressively shorter shift registers can convert the pipelined ADC output to parallel-bit form.

Abstract: A device for converting a signal voltage into a multi-bit digital word that efines the voltage magnitude and polarity. The input voltage V to be digitized is used to control the frequency of a voltage controlled oscillator, whose output is defined to be f=f.sub.o +kV. The signal out of the voltage controlled oscillator is fed to differential delay line filters that permit all digits to be derived in parallel. The filters comprise pairs of delay lines of unequal length, each pair feeding a respective phase detector whose output is amplified, and diode-rectified and limited. To increase the accuracy of this device, an automatic frequency control loop can be incorporated to control f.sub.o. This loop zeros V occasionally and reads the output digital word to measure the frequency error and add a correcting voltage to the input voltage V when it is not zeroed for the measurement.

Abstract: A monolithic digital-to-analog converter integrated circuit is disclosed including a first plurality of more significant bit switches having scaled bit switch currents and including a second plurality of lesser significant bit switches, the output nodes of which are coupled to a ladder network which contributes a binary-weighted portion of each lesser significant bit switch current to the summed analog output current. First and second output conductors, separate and apart from one another, are used to couple the output nodes of the more significant bit switches and the output current of the ladder network, respectively, to the analog output current pad. First and second ground voltage pads are included for isolating waste current conducted by the more significant bit switches from currents returned by the ladder network to the ground voltage. The waste current nodes of the lesser significant bit switches are conducted to the same ground voltage pad that conducts the currents returned by the ladder network.

Abstract: A method and apparatus for recursively generating an arithmetically compressed binary number stream responsive to the binary string from conditional sources. Throughput is increased by reducing the number of operations required to encode each binary symbol so that only a single shift of k bits is required upon receipt of each least-probable symbol or an "add time", followed by a decision and a one-bit shift in response to each most-probable symbol encoding. The concurrent augmentation of the compressed stream and an internal variable involves only the function of a probability interval estimate of the most-probable symbol, and not upon the past encoding state of either variable (2.sup.-k, 49, 63, C, T). Each binary symbol may be recovered by subtracting 2.sup.-k from the q-most-significant bits of the compressed stream and testing the leading bit of the difference.

Abstract: This invention relates to a signal conversion circuit, and more particularly to a signal conversion circuit to convert a digital signal sampled in synchronism with a sampling pulse into a pulse width signal having a pulse width corresponding to the digital value of the digital signal.A first counter is preset to a first count value corresponding to the digital value of the sampled digital signal and begins to count a first clock signal having a predetermined pulse period from the first count value. A second counter is preset to a second count value which is a complement of the first count value and begins to count a second clock signal having a pulse period twice as many as that of the first clock signal from the second count value in response to the detection of a full count of the first counter.