Abstract: A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment.

Abstract: A method and apparatus for recursively generating an arithmetically compressed binary number stream responsive to the binary string from conditional sources. Throughput is increased by reducing the number of operations required to encode each binary symbol so that only a single shift of k bits is required upon receipt of each least-probable symbol or an "add time", followed by a decision and a one-bit shift in response to each most-probable symbol encoding. The concurrent augmentation of the compressed stream and an internal variable involves only the function of a probability interval estimate of the most-probable symbol, and not upon the past encoding state of either variable (2.sup.-k, 49, 63, C, T). Each binary symbol may be recovered by subtracting 2.sup.-k from the q-most-significant bits of the compressed stream and testing the leading bit of the difference.

Abstract: A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test.

Abstract: A high accuracy monolithic digital to analog converter (DAC) which employs an EPROM controlled correction DAC to correct for errors in the output of a primary DAC. The correction DAC empolys a non-binary bit weighting which permits the use of low accuracy components in the fabrication of the correction DAC. The output of the primary DAC is skewed so that the required correction is always in a single direction, thereby eliminating the need for a constant offset generator. Resistors necessary for bipolar operation are included on the chip, thereby eliminating the need for connection of any external resistors to achieve such operation.

Abstract: A compressor parses the input data stream into segments where each segment comprises a prefix and the next symbol in the data stream following the prefix. The prefix of a segment is the longest match with a previously parsed segment of the data stream. The compressor constructs a search tree data base to effect the parsing and to generate a pointer for each segment pointing to the previous segment matching the prefix. The search tree comprises internal nodes including a root and external nodes denoted as leaves. The nodes are interconnected by branches representative of symbols of the alphabet. Each parsed segment of the input data is represented by a path from the root to a leaf. The tree is adaptively constructed from the input data such that as each new segment is parsed, one new internal node of the tree is created from a leaf and new leaves are defined, one for each symbol already encountered by the encoder plus an additional branch to represent all potential but unseen symbols.

Abstract: Carry-over control in strings resulting from the high to low order combining of two binary number strings is obtained through the insertion of a control character within the resultant string after detecting a run of consecutive 1's. Upon subsequent accessing and decomposition of the resultant string, the control character causes string decomposition to operate for a number of cycles in a carry correction mode. If the control character indicates that a carry has rippled through the n lesser significant positions of the resultant string, then upon decomposition, those "n" consecutive 1's are changed to 0's, and a 1 is added to the least significant position in the string preceding the control character. If the control character indicates no carry occurrence, then it is merely deleted from the string. The control of carries in this manner permits the generation of arithmetic string compression code sequences in an instantaneous FIFO pattern with only a modest reduction of compression efficiency.

Abstract: In a method of converting an analog input signal to a digital output signal, an analog input voltage is compared with two reference magnitudes which are invariable during the comparing. Both reference magnitudes are derived from an analog signal provided in a previous comparison by adding and subtracting a fixed magnitude representing a quantization step. Both reference magnitudes are simultaneously varied by increments or decrements equal to the steps when the analog input voltage is equal to one or the other of the reference magnitudes. Upon each variation, a pulse is emitted having a plus sign or a minus sign according to whether the analog input voltage reaches one or the other of the reference magnitudes. The number of pulses emitted is algebraically totalled thereby providing a digital indication of the mangitude of the analog input voltage.

Abstract: An analog-to-digital converter operable in sequential phases and including a main digital-to-analog converter (DAC) controlled by a successive-approximation-register to develop a first digital signal representing a first approximation of the analog input signal. In subsequent phases, the residual difference between the anolog input signal and the output of the main DAC is converted to a second digital signal representing the proportion which the residual signal bears to the difference between the first analog output of the main DAC and a second analog output of that DAC after it has been incremented by one least-significant-bit beyond the first DAC input developed in the successive-approximation phase. This proportioning operation is in one embodiment performed by a multiplying A-to-D converter, and in other embodiments is performed by an interpolation DAC. Microcomputer control of the various operations is disclosed.

Abstract: A plurality of resistance elements are connected via cutoff switches to form a ring. One of the connection points of each cutoff switch with the respective resistance element is connected via a feed switch to a common power source and via an output switch to a common output terminal. The other connection point of each cutoff switch with a resistance elements is connected via a grounding switch to a common potential point. An operation of turning OFF one of the cutoff switches, simultaneously turning ON the feed switch and the grounding switch on both sides of the turned-OFF cutoff switch, and turning ON the output switch selected in accordance with an input digital value, is repeated with a fixed period for all of the cutoff switches in a sequential order, while retaining the relative positions of the switches on the ring. By smoothing the output at the output terminal, scattered resistance values of the resistance elements are averaged.

Abstract: The present invention is directed to an improved method and apparatus for encoding binary data by which an improved sequence of encoded binary digits suitable for the NRZI modulation to produce a recording signal is obtained. The improved sequence of encoded binary digits obtained according to the invention consists of a plurality of binary digit blocks, each of which is formed with a predetermined number of the encoded binary digits obtained from the binary data and plural redundant codes, each of which is inserted between each successive two of the binary digit blocks, and can produce the recording signal forming a rectangular pulse train with the waveform which has the long minimum run length and does not contain the DC component or contains the diminished DC component therein when it is modulated in the NRZI modulation. By use of such a recording signal, high data density recording with a recording signal transmitted without distortions in its waveform can be achieved.

Abstract: In order to avoid errors due to time differences between output signals containing coarse bit information and fine bit information, an insertion circuit (77) is used in an analog-to-digital converter, having a coarse converter (5, 33) and two folding circuits (9, 13) which are each followed by a fine converter (19, 25, 33), to replace changing coarse bit information with changing fine bit information in the output signals.

Abstract: An analog data acquisition device fetches a plurality of analog data by a multiplexer in time-division, compares the analog data fetched with a reference value applied from a digital-to-analog converter by a two-input comparator, and produces the result of comparison to a data bus. The result of comparison is also applied to a successive approximation register where the analong-to-digital conversion is effected by successively changing the digital data to the digital-to-analog converter, and the digital data converted is read out onto the data bus.The digital data applied to the digital-to-analog converter is either the output from the successive approximation register or the output from the reference register loaded through the data bus, in accordance with the contents of the control register loaded through the data bus. Thus, in which mode the device operates, in the comparing mode or in the analog-to-digital conversion mode, is selected by the control register.

Abstract: A digital decoder for Miller encoded signals is disclosed comprising a resettable counter which is clocked at a frequency which is a large multiple of the base frequency of the Miller encoded signal. Transitions in the Miller encoded data stream are used to reset the counter. Digital signal storage means are provided for storing a digital signal having a value substantially equal to the value to which the counter is advanced in one Miller unit of time. Output logic circuit means responsive to outputs from the counter and digital signal storage means produces a binary output signal indicative of the decoded Miller encoded input signal. Means are provided for recurrently updating the contents of the digital signal storage means to adjust for variations in the base frequency of the Miller encoded input signal.

Abstract: A digital telecommunications system having an adjustable attenuation member incorporates first and second memories for altering the values of different pulse code modulated words, representing different amplitude values of transmitted waves, such as tone frequencies. One of the memories alters the first three amplitude bit values of a special pulse code modulated word to alter the values for example in six-dB steps. The other memory defines the values of smaller steps. The change of the output code from the first memory and the determination of the characteristic to be output by the second memory is dependent upon control signals from a control unit.

Abstract: Apparatus for generating clocking pulses from serially transmitted data in which a level shift recurs with each bit. The circuit uses a coincidence of data word recognition and initial level shift to generate an initial clock pulse and thereafter uses the delayed clock pulses and level shift to produce subsequent clock pulses. A data word recognition circuit is also disclosed that employs a delay line for examining the profile of a synchronizing wave form.

Abstract: A serial to parallel data conversion interface circuit is disclosed for certing a serial word supplied by a head tracker to a parallel word so as to allow for the processing of the parallel word by a microprocessor. The head tracker supplies to the interface circuit a data ready pulse signal. The interface circuit, in response to the data ready pulse signal, supplies a data acknowledge pulse signal and a clock signal to the head tracker so as to allow the serial word from the head tracker to be transferred to the interface circuit, which then converts the serial word to a parallel word. An enable pulse signal supplied to the interface circuit effects the transfer of the parallel word from the interface circuit to the microprocessor. A reset pulse from the microprocessor then resets the interface circuit so as to allow for the transfer of another serial word from the head tracker.

Abstract: An encoder for producing multidigit code word signals corresponding to the position and movement of a shaft or some other movable member, comprising a housing, a photocell board or some other signal producing board mounted on the housing and having photocell means or some other signal producing means including a multiplicity of signal channels for supplying a multiplicity of electrical signals indicating the position and movement of the code member, a plurality of circuit boards mounted on the housing in stacked relation to the signal producing board, the circuit boards including means for processing the signals from the signal producing means, and a multiplicity of sockets and pins mounted on the boards and plugged into one another for establishing electrical connections between the successive boards.

Abstract: Bi-polar electronic signal converters, such as analog-to-digital or digital-to-analog converters, with a single polarity accurate reference source are disclosed. In one polarity direction, the accurate reference source is used in a conventional manner to transform the signal to be converted from one form (e.g., analog) to the other form (e.g., digital). In the other polarity direction, an inaccurate reference source is used in a similar conventional manner to convert the signal from one form to the other form. Periodically, the accurate and the inaccurate reference sources are compared to determine a correction multiplier. The correction multiplier is used during conversions using the inaccurate reference source to compensate for the inaccuracy of the inaccurate reference source.

Abstract: An optical code disc includes a fine track which provides a high resolution signal, at least one V scan natural binary track synchronized to the fine track by lead and lag detectors, and Gray code tracks which provide the most significant bits of the digital output of the encoder system. The number of circuit elements in the multiplier circuitry associated with the fine track are reduced by means of a quadrant switching technique whereby the sinusoidal inputs to the multiplier are repeated through each quadrant of the fine track cycle. The V scan and Gray code tracks are optically multiplexed to reduce the number of leads from the optical detector. The use of both V scan and Gray code tracks minimizes the number of detectors required in the system while maintaining large detector signals from each track. The V scan and Gray code outputs are synchronized by the use of an overlapping bit.

Abstract: Means for converting characters of a first 128-character alphabet (ASCII) into characters of a second 26-character alphabet are provided and convert each pair of characters of the first alphabet into three characters of the second alphabet and vice versa.The means are embodied by a suitably programmed computer. In the conversion, each pair of characters Z.sub.1, Z.sub.2 of the first alphabet are interpreted as numbers and divided by 26. The resulting largest multiples Q.sub.1, Q.sub.2 of 26 are multiplied by 1 and 5 respectively and the products are added. The remainders after division give the first two characters A.sub.1 and A.sub.2 out of each set of three characters of the second alphabet, and the sum of the products gives the third character A.sub.3. Reconversion is similar. First, Q.sub.2 is obtained by division as the largest integral multiple of 5 in A.sub.3 and Q.sub.1 is the remainder after division. Q.sub.1 and Q.sub.2 are then each multiplied by 26 and added to A.sub.1 and A.sub.