Abstract: A non-binary digital encoding/decoding process wherein the serial bits to be transferred are encoded into a stream of complementary-bit-pairs, a predetermined bit of each pair corresponding to an original information bit, and the other bit of the pair being the complement of that bit. This stream of encoded complementary-bit-pairs is transferred, as by a communication or information-storage medium, to a decoder where the encoded stream is fed to and along a shift register. The bit-pairs in the decoder register are continuously examined for complementary relationship as the encoded stream is shifted along the register. The resulting signal generated in the decoder enables transferral of only error-free serial information out of the register, due to the error-detection properties inherent to the encoding/decoding process.

Abstract: An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.

Abstract: An optical displacement transducer for providing a digital output representative of the displacement of a variable from a datum value comprises a light beam emitter and a light beam receiver disposed on a common optical axis, a digital encoding element comprising an optical grating disposed between the light beam emitter and receiver, the grating extending in a circular path with the grating lines extending substantially radially of the path, means for causing relative rotation between the light beam and the grating about the center of the circular path whereby the light beam as seen by said receiver is in the form of a series of light pulses, a first reference position at a stationary position on the circular path, a second reference position on the circular path and angularly displaced about the center of the circular path from the first reference position whereby a predetermined light pulse count is produced during the relative rotation through the angle between the first and second reference positions, an

Abstract: A polarity-insensitive code converter in which blocks of binary digits are translated into multilevel words having either one mode or another mode so that each coded word of one block of binary digits is the inverse coded word of the block of inverse binary digits. Hence, the inversion of a code word during transmission results in the inversion of the recovered binary. With additional precoding and postcoding of the binary signal, polarity integrity of the original signal can always be restored.

Abstract: A digital scan converter is disclosed wherein signal information supplied by a sector scanning surveillance system relative to a polar coordinate system is converted to a signal for driving a television-type display or other Cartesian coordinate device by: (a) sampling the signal associated with each consecutive scanning path of the surveillance system at a rate determined by the azimuthal angle that defines the scanning path of interest; (b) storing each set of signal samples as a column of data in a rectangular memory array; (c) accessing the stored data on a row-by-row basis; and (d) utilizing a previously determined mapping strategy to cause each accessed signal sample to form a segment of a line of display within the Cartesian-formulated display devices so that the length of the segment formed by each signal sample is determined by the row and column address of the storage location that is associated therewith when forming a television compatible signal, each signal sample dictates video signal level dur

Abstract: A direct flash converter has independent parallel analog-to-digital encoders for each bit. Cross-coupled level sensors are coupled to a single comparator within each bit encoder to provide a directly encoded Gray code binary output.

Abstract: In a delta modulation coder and decoder system, the disadvantageous effects of slope overload are eliminated by reversing the polarity of the feedback signal in the coder and the polarity of the reconstructed analog signal in the decoder whenever slope overload correction is required. This is accomplished by the addition, to both the coder and decoder, of control circuitry which determines whether slope overload correction is required. To make the determination, first the digital output signal of the coder is tested to determine whether its rate of change is equal to a maximum value. Second, the magnitude of the feedback signal is tested to see if it lies below a threshold value. If both these conditions are satisfied, slope overload correction is then performed.

Abstract: An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A-and Mu-255 law PCM conversion capability.

Abstract: An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A- and Mu-255 law PCM conversion capability.

Abstract: In an integrated circuit type dual ramp analog to digital converter (10), the duration of the reference voltage integration, or ramp-down period, is precisely determined to control count accumulation in an external output counter (32a) operating in parallel with the standard internal counter of the integrated circuit. A reference voltage is stored on a flying capacitor (50) that is polarity switched, depending upon the polarity of the input signal, to be applied to the input of an integrator (12) during the ramp-down period. To establish the beginning and end of ramp-down, one end (52) of the flying capacitor (50) is applied to a comparator (54). As the voltage at the monitored end of the flying capacitor (50) undergoes abrupt level changes at the end points of the ramp-down interval, the comparator (54) generates start and stop pulses to the external output counter (32a).

Abstract: A latchable bit switch for use in a digital-to-analog converter comprising four differential pairs of transistors and a capacitor. The first pair are responsive to a digital input signal and an inverse digital input signal while the second pair are cross coupled and are responsive to the output of the first pair. The third pair are responsive to a toggle signal and a latch signal and enable either the first or second pair. The fourth pair are responsive to the output of the first and second pair and enable a bit current to a summing bus. The capacitor is coupled across the output of the first and second pair thereby reducing glitches in the bit current caused by the charging of junction capacitances by the fast transitions of the digital input, toggle, and latch signals.

Abstract: An apparatus and method for decoding input signals on four lines to produce an outgoing information stream of binary bits.

Abstract: A monolithic integrable R-2R resistor network comprises a number of series resistors connected to a terminal resistor; and a plurality of 2R resistor units each capable of being switched by two electronic switches either to ground or to another reference point, a different plurality of 2R resistor units being coupled to the nodes between each of the series resistors, to the node between the terminal resistor and the last resistor of the series resistors and to the node ahead of the first resistor of the series resistors. To compensate for the effects of the variations of the switch resistances caused during manufacture by process parameter fluctuations upon the accuracy of a D/A converter, a switch structure is inserted at each of the nodes which, with respect to the two electronic switches, is of the same kind, and which is permanently in an electrically conducting state.

Abstract: A successive-approximation charge-redistribution analog-to-digital converter includes a binary weighted capacitive ladder for converting the least significant bits of the binary output representation and a resistive ladder for converting the higher order bits of the output representation. To achieve a half least significant bit shift, the capacitor of lowest capacitance in the ladder having a capacitance C is replaced by first and second capacitors each having a capacitance C/2. Each of these capacitors has a first terminal connected to the input of a comparator. Another input of the first capacitor is coupled to the low reference voltage. The second input of the second capacitor is coupled to one-eighth the high reference voltage during the sample phase and to the low reference voltage when the sample phase is completed. The resulting redistribution of charge which occurs at the input to the comparator is equivalent to minus one-half times the charge corresponding to one least significant bit.

Abstract: A linear interpolator comprising a code digital normalization unit, connected via digital-to-analog converters to comparators which couple an adjustable reference voltage source, and also connected via an OR gate to an integrator that connects said digital-to-analog converters having their outputs coupled respectively to X- and Y-axis voltage-to-frequency converters, the latter being connected to control circuits of actuation means.

Abstract: Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount .DELTA.DC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the .DELTA.DC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.

Abstract: Successive frames of spliced-together exposed and developed photographic films are examined prior to introduction into a copying machine to prevent the reproduction of film frames having blurred images. Portions of or entire film frames at an examining station are spot scanned, line-by-line, and the resulting video signals are processed to determine one or more quotients which denote the ratio of maximum density gradient to density range of the respective film frames, the ratio of first and second density gradients obtained on scanning the entire frequency spectrum or the lower density portion of a film frame, and the ratio of frequency of occurrence of the first and second density gradients. Such quotient or quotients are compared with a threshold value and the results of comparison are used to classify the film frames as suitable or unfit for the making of reproductions.

Abstract: Disclosed is a digital signal processing circuit, which can process digital data of at least two different data formats where one word consists of respectively of m and n bits (m and n being positive integers and m>n), for instance 16 and 14 bits, resides in that serial data of the data format where one word consists of m bits (for instance 16 bits) is rearranged into a form conforming to the data format where one word consists of n bits (for instance 14 bits) and that processing (for instance T matrix calculation) is effected according to a bit clock corresponding to the difference in the bit number between m and n, thereby obtaining data conforming to the data format where one word consists of n bits.

Abstract: An analog to digital conversion circuit of the stage by stage, successive approximation type which incorporates a plurality of cascaded stages.

Abstract: A rotary shaft position measurement system using digital position detectors roviding coarse and fine binary word readouts having four overlapping bits all of which are having subtractively compared to provide command signals that are used to correct the non-overlapping portion of the coarse word prior to combining with the fine word. The comparator utilizes a binary four bit full adder in combination with coarse word input inversion, and direct and inverted application of the carryout and .SIGMA.4 outputs to first and second AND gates to generate coarse word correction commands.