Abstract: The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

Abstract: A method for manufacturing a semiconductor device of the present invention comprises the following steps (1) through (7) of, (1) forming a lower insulation film thicker than a metal wiring layer to be formed in order on a semiconductor substrate, a first conductive film and an upper insulation film; (2) removing the upper insulation film in the wiring formation area and then exposing the lower insulation film by etching the first conductive film; (3) forming concave grooves in the lower insulation film by etching the film using as a mask the upper insulation film whose wiring formation area is removed or a photoresist applied to the patterning of the upper insulation film; (4) forming a second conductive film on the whole surface including the concave grooves and successively forming sidewalls made of the insulation film in the sides of the grooves; (5) forming metallic wiring layers by electrolytic plating in the grooves wherein the said sidewalls have been formed by electric power supplied from the second c

Abstract: Selective salicidation of source/drain regions of a transistor is accomplished by differentially treating a first subset of the source/drain regions to hinder formation of metal-silicide over the first subset of the source/drain regions. A metal layer is formed over the first subset of the source/drain regions and a second subset of the source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second subset of the source/drain regions, but not over the first subset of the source/drain regions. The unreacted metal is stripped off over the first subset of the source/drain regions. In the preferred embodiment of the present invention, a second anneal is then performed to fully form metal-silicide over the second subset of the source/drain regions.

Abstract: An improved barrier, and a method for forming such a barrier, between a semiconductor substrate and a metallized contact. A first metallic layer is deposited over the substrate and the contact well formed therein. The first metallic layer is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer is deposited over the first stuffed metallic layer. A third metallic layer is then deposited over the second metallic layer. An anti-reflective fourth layer of metal is then deposited over the third metallic layer. The exposure of the first metallic layer to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Therefore, the present invention eliminates the need for time-consuming pressure breaks. As a result, the throughput of the present invention is substantially increased over prior art barrier formation processes.

Abstract: A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

Abstract: A method for forming a multi-level wiring structure for semiconductor devices includes the steps of forming inter-layer insulating films and exposing at least a part of such films to a vapor containing alkoxyfluorosilane. This enables the water content of silicon oxide films to be reduced, the quality thereof to be made higher and the production yield and the reliability of the product to be enhanced. The method for forming an insulating film includes the steps of exposing such film to a vapor containing alkoxyfluorometal as a major component and heat-treating the exposed film. The method for forming a surface protective film includes the steps of forming a silicon oxide film at a temperature of 250.degree. C. at most, applying to such film a coating solution for SOG, heat-treating the film at a temperature of 200.degree. C. at most, exposing the film to a vapor containing alkoxyfluorosilane as a major component, heat-treating at a temperature of 250.degree. C.

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.

Abstract: A first conductive film which is formed on both an insulating film and a field insulating film is covered by a buffer insulating film. After that, an opening is formed through from a region on the semiconductor substrate to a region on the field insulating film by patterning the insulating film, the first conductive film and the buffer insulating film. Then, the surface of the semiconductor substrate in the opening is processed by using vapor-etching method. Lastly, the second conductive film connected to the semiconductor substrate in the opening is formed. When vapor-etching, the buffer insulating film remains around the opening, so that a etchant is supplied uniformly. Thereby, excessive etching is restrained, then the field insulating film with sufficient thickness remains in the opening. Also, the natural oxide in the opening has been exposed to the etchant from the first stage of etching, so that the natural oxide is securely etched and removed.

Abstract: A method of manufacturing a semiconductor device which comprises steps of forming a diffusion region to a semiconductor substrate; forming silicon compound film on the diffusion region; forming a metal film on the silicon compound film to form a metal silicide film and, further forming an interlayer film; forming a barrier metal material film on the interlayer film; then patterning the barrier metal material film to obtain a barrier metal layer, subsequently; patterning the interlayer film to form a contact hole and burying a wiring material into the contact hole thereby forming a wiring.

Abstract: A process for producing a plurality of metallized vias in a polyimide dielectric is disclosed. The process includes depositing a polyimide precursor, then a silane and finally a metal, after patterning the polyimide and silane. The sandwich is heated to completely imidize the polyimide, crosslink the silane and anneal the metal simultaneously. The excess metal overlying the polyimide between the vias is removed by chemical mechanical polishing using the crosslinked silane as a polish stop.

Abstract: A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via combining TEOS with ozone silicon oxide pyrolytic deposition with plasma-enhanced deposition processes and spin-on-glass processes. A first insulator layer is provided over the conductive layer by plasma-enhanced chemical vapor deposition (PECVD). This insulator layer is covered with a layer of TEOS with ozone deposited silicon oxide by pyrolytic chemical vapor deposition (THCVD). The TEOS with ozone silicon oxide layer will fill the irregular trenches and holes in the conductive layer structure not filled by the first insulator layer. The TEOS with ozone layer is anisotropically etched back leaving the TEOS with ozone layer only in the trenches and holes of the layer structure. A second insulating layer is deposited by PECVD and then is covered by at least one spin-on-glass layer to fill the wider valleys of the irregular structure.

Abstract: A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate.

Abstract: A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26).

Abstract: A method substantially eliminating consumption of silicon from semiconductor devices is provided. The method includes controlling gases within the environment wherein the semiconductor device is positioned. The environment is formed to include an inert gas and oxygen. The oxygen content is formed to have a concentration between approximately 1.times.10.sup.1 and 1.times.10.sup.5 parts per million. Such an oxygen concentration substantially prevents converting silicon from the semiconductor device into silicon monoxide thereby substantially eliminating silicon consumption.

Abstract: The present invention relates to detergent compositions comprising a glyceroglycolipid having one or two ether linkages for use as a surfactant or cosurfactant in the detergent compositions.

Abstract: A process for etching narrow features, particularly submicron borderless contacts, in a semiconductor substrate is disclosed. The process comprises depositing, by an orientation-sensitive technique, film which will act as an etch stop. The film is significantly thicker on horizontal surfaces than on vertical. A second layer is deposited and then etched using the first film as an etch stop. In one embodiment the etch stop is composed of an oxidizable material.

Abstract: A transition-metal silicide process includes the formation of a boron nitride capping layer overlying a transition-metal layer. In one embodiment, a transition-metal layer (30) is deposited onto a silicon surface (22), and onto a polysilicon gate electrode (12). A capping layer (32), which can be either boron nitride or boron oxynitride is deposited onto the transition-metal layer (30), and an annealing process is carried out to form a transition-metal/silicon alloy layer (34, 36, 38) at the silicon surface (22), and on the gate electrode (12). The capping layer (32) overlies the transition-metal layer (30) during the annealing process and prevents the formation of an oxide layer at the silicon surfaces (22, 12). After the annealing process is complete, the capping layer (13) is removed by a selective wet etch process, and a second annealing step is carried out to form a transition-metal silicide layer (40, 42, 44).

Abstract: The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as titanium nitride) to the aluminum bond pad by chemical vapor deposition or by electroless deposition; and adhering a conductive epoxy film to the metal layer, thereby forming a low resistive bond pad interconnect.

Abstract: A method of making integrated circuit chip to substrate connections first deposits a blanket layer of CrCu over a completed wafer which has terminal vias etched in the final insulator. Then PbSn solder is electrolytically plated through a photoresist mask. After the plating is done, the resist is removed and the Cu is etched using the solder dot as a mask, and then the solder dots are melted to form spheroid or ball shapes. Next, a positive photoresist is applied in a manner that distributes the photoresist around the base of the solder balls. The solder balls are then used as a self-aligned exposure mask. Since the photoresist under the balls is not exposed, each ball has a concentric layer of resist at the base after exposure and development. This concentric layer of resist protects the Cu/PbSn interface and is used as the mask for etching excess Cr. The resist is then removed.

Abstract: A method of manufacturing a separator for forming a current collector and edge plate by placing a die and an outer frame for surrounding the die on a press head, placing a thin material plate and a soft plate, and pressing the thin material plate through the soft plate. When the current collector and the edge plate are made press working, cut working and joint working such as welding, can be omitted. Accordingly, the residual stress which is intrinsic to such workings is prevented. Thus, no stress is released by the temperature rise involved in the fuel cell operation and the members of the fuel cell do not become distorted. Additionally, the method provides high productivity.