Abstract: A method and structure for a titanium tungsten (TiW)/tungsten local interconnect (136) for cells (100) of semiconductor device includes steps and structure resulting from sputtering a titanium tungsten (TiW) layer (128) on semiconductor structure (100) and then forming a tungsten layer over the TiW layer (128). Then, the method is to pattern a layer of resistive polymer (32) such as photoresist in a predetermined lithographic pattern over the structure (100). This forms the local interconnect (136) from the TiW layer (128). Then, by dry etching, the process removes exposed portions of the tungsten and TiW layers. A wet strip process removes resistive polymer (32) from the semiconductor structure (100) to yield TiW/tungsten interconnect (136) for the semiconductor structure (100). Alternatively a single TiW layer is used in which exposed portions of the TiW layer are removed by a wet etch.

Abstract: A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.

Abstract: An improved method of filling vias and openings in semiconductor devices comprises first faceting the top of the openings, depositing in sequence a barrier layer, as of TiN, treating the barrier layer to reduce its porosity, depositing a titanium-containing wetting layer, sputter depositing a first layer of aluminum at low temperatures and sputter depositing a second layer of aluminum at high temperatures to fill the opening and planarize the layer. The improved method is carried out preferably in a multichamber sputtering system.

Abstract: A method and apparatus for providing a substantially constant output voltage from a fuel cell, notwithstanding output current variations, is disclosed. The voltage and secondarily the current of the cell is determined at least periodically. The pressure of the reactant gas in the fuel cell is then regulated so substantially the nominal voltage is maintained. The temperature in the fuel cell may also be regulated to maintain the nominal output voltage. Also, a method and apparatus for minimizing the parasitic power drain in a electric power generation system is disclosed. The fuel cell is fed with an reactant gas by a compressor driven by parasitic power drawn from the fuel cell.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: A method for forming electrodes with strong adhesion strength for a semiconductor device is provided. The adhesion strength between a Si substrate and a Ti film is made higher than the pulling stress of a Ni film. Before an electrode is formed using sputtering process, the natural oxide film grown on a semiconductor substrate is removed using an Ar reverse sputtering while the top surface of the silicon substrate is converted to an amorphous through a bombardment and introduction of Ar. While Ti is deposited, a Si-Ti amorphous layer is formed in the Si/Ti interface. In this case, the amount of Ar atoms is controlled less than 4.0.times.10.sup.14 atoms/cm.sup.2. The Ar amount also can be controlled by adjusting the conditions such as the output or cathodic voltage of Ar reverse sputtering and decreasing the absolute value of Ar in the amorphous Si layer. Also the Ar amount can be controlled by diffusing Ar atoms into the substrate at more than about 300.degree. C.

Abstract: A method and system for fabricating semiconductor wafers is disclosed wherein an atomically clean, semiconductor substrate having a surface is provided in a rapid thermal processing chamber. One embodiment involves cleaning the substrate by exposing it to a first gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 10 to 60 seconds. Subsequently, a coating having a first thickness is formed superjacent the substrate surface by introducing a second gas at a temperature substantially within the range of 850.degree. C. to 1250.degree. C. for approximately 5 to 30 seconds in the chamber. The resultant coating, depending on the gas selected, comprises either SiO.sub.2 or Si-F.Subsequently, the substrate having the coating is exposed to a third gas at a temperature substantially within the range of 900.degree. C. to 1050.degree. C. for approximately 30 minutes to one hour, thereby forming a silicon dioxide layer.

Abstract: A semiconductor device includes a semiconductor substrate, an active layer formed on the semiconductor substrate, source and drain electrodes respectively formed on the active layer, a gate electrode formed on the active layer between the source and drain electrodes and including a gate contact portion which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, a first insulator layer formed on the active layer and covering the source and drain electrodes and the gate contact portion, a first contact hole in the first insulator layer through which the overgate portion connects to the one of the source and drain electrodes, a second insulator layer formed on the first insulator layer and covering the overgate portion, a second contact hole in the second insulator layer at a position above the overgate portio

Abstract: A process for producing a leadframe for a semiconductor including (i) providing nickel or nickel-base alloy plating layers on both sides of a base material including an iron-base material or a copper-base material by electroplating or chemical plating so as to have a single layer thickness in the range of from 3 to 20 microns, (ii) applying a photoresist on both sides of the leadframe material produced in step (i) and forming a leadframe pattern by a patterning process and (iii) subjecting the leadframe material patterned in step (ii) to etching.

Abstract: The present invention relates to a manufacturing method of a contact of a multi-layered metal line of a highly integrated semiconductor device.The insulating layer between the metal lines is flattened and step coverage is improved by using a SOG layer or polyimide.

Abstract: A metal-air power supply which provides improved control over air flow is provided. The reactant air and cooling air inlets are separate from one another and isolated from the exhausted reactant and cooling portions of the air flow. The reactant air flow is limited to a volumetric flow rate sufficient to provide from about 3 to about 10 times the stoichiometric amount of oxygen necessary to produce a predetermined level of current from the cell, and a total volumetric flow rate of air sufficient so that the cooling portion of the air flow has a volumetric flow rate from about 10 to about 1000 times the volumetric flow rate of the reactant portion of the air flow is provided.

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Abstract: A method for fabricating an interconnect structure in an integrated circuit. A first conductive layer is formed over an underlying region in the integrated circuit. The underlying region may be, for example, a semiconductor substrate or a gate electrode. A buffer layer is then formed over the first conductive layer, followed by the formation of an insulating layer over the buffer layer. The insulating layer and the buffer layer are patterned to define a form for the interconnect structure. A second conductive layer is then formed over the integrated circuit, and portions of the first conductive layer, the second conductive layer, and the buffer layer are silicided to form the interconnect structure.

Abstract: A method of fabricating a semiconductor device in which first an aluminum film is etched using a photoresist pattern as a mask, and then the patterned aluminum film is used as a mask for plating to form a pattern of gold plating film. In so doing, if a wiring is formed using a plating process, the problems of deformity of the gold plating film due to degradation of a plating solution, short-circuits between the patterns due to cracks in the plating mask, and re-adhering of etched material when etching the electrical current paths used during the electroplating process, and the problem of sideways etching can be solved.

Abstract: A method of fabricating a multi-layered interconnection structure which comprises the steps of: forming a first wiring layer on a silicon oxide film having a compressive stress; forming a thick (2 to 3.5 .mu.m) fluorine-containing silicon oxide film at a temperature not higher than 200 .degree. C.; etching back the fluorine-containing silicon oxide film to flatten the surface of the film; forming a silicon oxide film having a compressive stress; forming a through-hole in position; and forming a second wiring layer. Since the fluorine-containing silicon oxide film is used as part of an insulating film, a resistance to cracking, flatness and reliability are significantly improved.

Abstract: An improved aluminum wired layer for interconnecting a device to another device and which comprises a plurality of aluminum wired layers formed on an insulating layer of a semiconductor device and the method of manufacturing such aluminum wired layer is disclosed. The improvement of the aluminum wired layer comprises a plurality of aluminum wired layers positioned on the insulating layer, with each aluminum wired layer being spaced relative to each other and having a top, side walls and a bottom. A first Al-Ti compound metal layer is formed on the top and on the side walls of each aluminum wired layer to prevent the formation of hillock on the surface of each aluminum wired layer during the heat treatment process and to prevent electromigration phenomenon in each aluminum wired layer when the semiconductor device is in operation.

Abstract: A new method of forming polysilicon buried contact to source/drain or emitter regions is described. A silicon oxide layer is formed over the silicon substrate. An opening is formed to the silicon substrate at the location of the desired buried contact to source/drain or emitter region via conventional techniques. A hydrofluoric acid solution is used to remove the native silicon oxide which forms on the exposed surface of the silicon substrate. Some native silicon oxide is formed in a controlled manner again on the surface of the silicon substrate. The wafer is put into a low pressure chemical vapor deposition (LPCVD) apparatus and a layer of undoped polysilicon or amorphous silicon is deposited. An oxidizer is added to the deposition chamber or the wafer is exposed to ambient air so that a thin layer of native silicon oxide is formed in a controlled manner overlying the polysilicon layer. Additional alternating layers of polysilicon and native silicon oxide are formed as desired.

Abstract: A method for cleaning a chemical vapor deposition (CVD) process for depositing tungsten. After the tungsten has been deposited and the wafer has been removed from the chamber, the chamber undergoes an in-situ cleaning process. In the currently preferred embodiment the in-situ cleaning process consists of cleaning the chamber with nitrogen tri-fluoride (NF.sub.3) and hydrogen (H.sub.2) nitrogen (N.sub.2) plasmas. The tungsten CVD cleaning process also includes purging the chamber with the dilute mixture of silane (SiH.sub.4), argon (Ar) and nitrogen (N.sub.2).

Abstract: A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Abstract: A method for preparing a free flowing perfume capsule composition with enhanced performance and stability from slurries containing perfume capsules is described. A process comprising removing water from the slurry to form a wet cake, combining silicone dioxide or aluminosilicate to the wet cake to fluidize the wet cake and removing additional water from the fluidized wet cake to form free flowing perfume capsules is preferred.