Abstract: A method of forming a metal pattern on a substrate. The method includes depositing an insulative nitride film on a substrate and irradiating a laser beam onto the nitride film, thus decomposing the metal nitride into a metal constituent and a gaseous constituent, the metal constituent remaining in the nitride film as a conductive pattern.

Abstract: A process for fabricating a device having a TiW barrier layer and a relatively shallow junction contacted with a silicide layer wherein said TiW barrier layer and said silicide layer are simultaneously formed comprising steps of preparing a Si substrate, applying a layer including therein a Ti and an appropriate X element such as Co or Pt on the Si substrate, applying a W layer on the layer including therein the Ti and the X element for forming a W/X-Ti/Si structure, and transforming the W/X-Ti/Si structure into a TiW/silicide/Si structure to obtain the device having a TiW barrier layer and a silicide layer contacted shallow junction. The present invention provides a simplified process for fabricating such a device having therewith a junction of a low resistance and a high temperature stability.

Abstract: A monolithic integrated circuit capable of operation in the microwave range which is fabricated using silicon technology wherein transmission line interconnects are fabricated along with active devices on the same substrate. The transmission line is provided using polycrystalline silicon since it can have much higher resistivity than single crystal silicon. Accordingly, a circuit is provided wherein active devices are provided in single crystal silicon and interconnects are formed overlying polycrystalline silicon to provide transmission line interconnects between devices and obtain the desired high frequency response.

Abstract: Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

Abstract: A method of manufacturing liquid-crystal elements having two substrates on the surface of which a electrode group formed of stripe-shaped transparent electrodes and a metallic wiring pattern, and a liquid-crystal layer sandwiched between the two substrates, the method including the step of: repairing residue defects of the lower layer first and next residue defects of the upper layer by using etching solutions for selectively etching the transparent electrode or the metallic wiring pattern when etching residue defects between the stripe patterns of the transparent electrode and the metallic wiring are repaired.

Abstract: A method of forming a metal-disilicide (MSi.sub.2) film from a silicon-on-insulator (SOI) substrate having an insulating underlayer and a silicon outerlayer includes the formation of a first capping layer on a portion of the silicon outerlayer. The first capping layer preferably includes titanium and a preselected metal (M) such as cobalt. A step is then performed to convert a first portion of the silicon outerlayer to metal-disilicide. This step is preferably accomplished by a rapid thermal annealing step. Thereafter, a second capping layer is formed on the metal-disilicide layer. The second capping layer preferably includes titanium and metal-monosilicide (MSi). Next, a step is performed to convert a second portion of the silicon outerlayer, beneath the first portion, to metal-disilicide while preventing phase-reversal of the already formed metal-disilicide layer to metal-monosilicide. This step is preferably accomplished by a rapid thermal annealing step as well.

Abstract: A silicon nitride layer (34) has improved adhesion to underlying copper interconnect members (30) through the incorporation of an intervening copper silicide layer (32). Layer (32) is formed in-situ with a plasma enhanced chemical vapor deposition (PECVD) process for depositing silicon nitride layer (34). To form layer (32), a semiconductor substrate (12) is provided having a desired copper pattern formed thereon. The copper pattern may include copper interconnects, copper plugs, or other copper members. The substrate is placed into a PECVD reaction chamber. Silane is introduced into the reaction chamber in the absence of a plasma to form a copper silicide layer on any exposed copper surfaces. After a silicide layer of a sufficient thickness (for example, 10 to 100 angstroms) is formed, PECVD silicon nitride is deposited. The copper silicide layer improves adhesion, such that silicon nitride layer is less prone to peeling away from underlying copper members.

Abstract: The present invention teaches a method for fabricating an ultrathin uniform dielectric layer over a silicon or polysilicon semiconductor substrate. The method entails first providing a substrate having a conductive area into a chamber. Subsequently, the first conductive material is destabilized by introducing it to reactive gas and radiant energy in situ. The reactive gas can be Ar-H.sub.2, H.sub.2, GeH.sub.4 or NF.sub.3 gas. The radiant energy source can be ultraviolet ("UV") or Tungsten Halogen lamps preferably having an approximate range of 0.2 to 1.6 .mu.m to provide heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. This process removes the native oxide and breaks the molecular clusters present on the silicon or polysilicon surface. Thereafter, a first dielectric layer having a substantially uniform thickness forms directly above the substrate by the in situ introduction of NH.sub.

Abstract: A method for forming custom planar connections to the bonding pads of a semiconductor die is provided. The method includes the steps of: depositing a passivation layer on the bonding pads; forming a patterning layer by depositing a dielectric material such as TEOS on the passivation layer; etching through the patterning layer and passivation layer to the bond pads using a first etch mask; etching a connector pattern in the patterning layer using a second etch mask; depositing a metal layer over the patterning layer; and then planarizing the metal layer to an endpoint of the patterning layer to form planar metal connectors having a desired thickness.

Abstract: A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

Abstract: An electrochemical process for energy storage and/or power generation and apparatus comprises cell array of unit cells (10), each cell comprising a +.sup.ve electrode (12) and a -.sup.ve electrode (14) with a membrane in each cell dividing it into +.sup.ve and -.sup.ve chambers (22C and 24C) for catholyte and anolyte solutions (22, 24) which are recirculated through separate pumps (26, 28) and storage tanks (32, 34) and back to the chambers. Mid electrodes, between adjacent cells in the array, provide both a +.sup.ve side and a -.sup.ve side. A bromine-sulfur couple may be employed.Means are provided to compensate for pH changes and/or changes in hydroxyl ion concentration in the +.sup.ve and/or the -.sup.ve sides of the array of cells.

Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800.degree. C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.

Abstract: A method for self-aligned zero-margin contacts to active and poly-1, using silicon nitride or other dielectric material with low reflectivity and etch selectivity to oxide for an etch stop layer and also for sidewall spacers on the gate.

Abstract: Tungsten studs and tungsten lined studs that make low resistance thermally stable ohmic or Schottky contacts to active devices on a semiconductor substrate are made by first defining a triplex metallurgical structure. The triplex metallurgical structure includes an ohmic layer, a barrier layer and a sacrificial layer. Then, a blanket layer of insulator is deposited and polished, or etched, or both, until the stud metallurgy is exposed. The sacrificial layer is then etched out, leaving holes self-aligned to the contacts and to the ohmic and the barrier layers. A blanket layer of CVD tungsten is then deposited and the substrate is polished, or etched, or both, to remove excess tungsten. The metal contact studs can be simultaneously formed with patterned interconnection lines which are self-aligned to each other and also to the contact studs.

Abstract: A method for forming interconnects in an integrated circuit chip which includes a plurality of active devices over which a layer of dielectric material is deposited. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines; (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper.

Abstract: A process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided. A thin insulating layer is formed on the surface of a substrate. Next, a blanket conductive layer and a blanket masking layer are deposited over the first insulating layer. Using conventional photolithography processes and plasma etching, elongated spaced parallel masking lines with vertical sidewalls are formed in the masking layer. A blanket polycrystalline silicon layer is deposited on the masking lines and the exposed areas of the conductive layer. Next, the blanket polycrystalline silicon layer is anisotrophically etched to form spacers on the vertical sidewalls of the masking lines. A second planarized masking layer is formed over the spacers and masking lines. The polycrystalline silicon spacers and the underlying first polycrystalline silicon layer are anisotrophically etched to form the closely spaced conductive lines in the first polycrystalline silicon layer.

Abstract: A thin-layer metallization structure in which the final gold layer is deposited by evaporation with the surface onto which it is evaporated maintained at an elevated temperature. By evaporating the uppermost gold layer of the structure at an elevated substrate temperature, the gold atoms have a higher mobility, causing the deposited gold to spread over the edge of the structure and cover the otherwise exposed edges, including the edge at the copper interface.

Abstract: Polyhydroxypolyethers as low foam surfactants comprising a compound of the general formula ##STR1## wherein R.sup.1 is a linear or branched C.sub.2 - to C.sub.18 -alkylene radical;R.sup.2 is H, ##STR2## R.sup.3, R.sup.4 are linear or branched C.sub.2 to C.sub.18 alkyl radicals;Z is a number of from 1 to 3;with the proviso that at least one R.sup.2 is ##STR3## n is a number of from 2 to 8; m is a number of from 15 to 34; andl is a number of from 0 to 3.These compounds are useful in cleaning compositions and rinse aids which are low foaming and biodegradable.

Abstract: A process for laser processing an article, which comprises: heating the intended article to be doped with an impurity to a temperature not higher than the melting point thereof, said article being made from a material selected from a semiconductor, a metal, an insulator, and a combination thereof; and irradiating a laser beam to the article in a reactive gas atmosphere containing said impurity, thereby allowing the impurity to physically or chemically diffuse into, combine with, or intrude into said article.

Abstract: In a method for making contact holes in a semiconductor device according to the invention, a first insulating film is deposited on a semiconductor chip, a plurality of contact holes are formed by sequentially performing isotropic etching and anisotropic etching, a second insulating film is deposited after the portions of the first insulating film constituting peripheries of the contact holes are subjected to a reflow process, and residue sidewall insulators are formed for the contact holes by keeping portions of the second insulating film only at sidewall portions of the contact holes when the second Insulating film is etched-back by an anisotropic etching process. The structure thus obtained enables to provide the contact holes whose peripheral edges are gently tapered thereby improving the step coverage of the Interconnect wiring material at the contact hole portions.