Abstract: A bilayer thin film resistor and a method of fabricating such as resistor. A layer of a resistive material such as titanium tungsten is sputter deposited on a substrate before depositing a relatively thick overlayer of a material such as chromium silicon monoxide to form a bilayer resistor. Whereas the sheet resistance of a chromium silicon monoxide layer by itself would be relatively unpredictable and unreproducible, the sheet resistance and the uniformity of the bilayer can be accurately controlled by making small adjustments to the scan rate of the titanium tungsten to control the thickness of the underlayer. Optionally, the titanium tungsten underlayer can be sputter etched to increase to sheet resistance of the bilayer, and also to increase heat stability so as to decrease the drop in sheet resistance during subsequent thermal processing.

Abstract: The present invention relates to a method for personal cleansing with rinse-off compositions comprising certain foam enhancing polymers in an aqueous solvent system. These compositions, when delivered from an aerosol or non-aerosol system, produce aesthetically preferred foam in copious amounts.

Abstract: A new method of forming the passivation layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed having a metal line layout in which the metal lines have a fixed spacing throughout their length and larger width around a turn than they have throughout the remainder of their length. Metal islands are formed perpendicular to the metal lines at the terminals of the metal lines. Dummy vias are opened in the insulating layer at the terminals of the metal lines wherein the terminals of the metal lines fill the dummy vias thereby reducing the aspect ratio of the spacing of said metal lines. A passivation layer is deposited over the metal lines wherein tunnels are formed within the passivation layer between the metal lines and at the terminals of the metal lines. The metal layout of the present invention prevents openings from being made within the passivation layer to the tunnels.

Abstract: The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

Abstract: An object of the present invention is to realize a method of and equipment for manufacturing a semiconductor device which can improve the flatness of an interlayer insulating film and increase the reliability of the metal wiring of a second layer to be formed in a succeeding process. The method of manufacturing the semiconductor device of the present invention is characterized by a manufacturing process to be successively implemented comprising: a step for forming an insulating film by means of a chemical vapor deposition method on a semiconductor substrate having an electrode patterned thereon; a step for selectively removing the insulating film by using a reactive ion etching method and forming a side wall made of the insulating film on the patterned electrode; and a step for forming the insulating film by means of the chemical vapor deposition method while introducing excited halogen molecules at an excited molecule oscillation level.

Abstract: This invention relates to the encapsulation of active ingredient within polymeric material so as to protect the active ingredient from the ambient environment, for instance atmospheric moisture when the product is exposed to the air, or the liquid phase of a liquid detergent when the product is incorporated in such a detergent. A dispersion in oil of an aqueous solution of a matrix polymeric material containing enzyme or other active ingredient is subjected to distillation to provide a substantially anhydrous dispersion in oil of particles of matrix polymer containing active ingredient, and during or after the distillation the polymer solution is converted into a solid polymer. In the invention, we use a matrix polymer that is so hydrophobic that it partitions preferentially into the oil rather than into the aqueous solution of encapsulating polymer.

Abstract: A method for the construction of a highly integrated semiconductor connecting device. In the semiconductor connecting device, a plurality of third conductive lines are connected with a plurality of first conductive lines formed in the active regions of a semiconductor substrate through contact holes formed on the active regions, passing by and being insulated with a plurality of second conductive lines which are intercalated between a first interlayer insulating film and a second interlayer film and which are formed above a plurality of device separation insulating films formed in the semiconductor substrate. With the method, a stepped part is avoided thereby eliminating a cause of a the short circuit caused by remnant conductive material. In addition, the charge storage electrodes are connected with the source electrodes, while being securely disconnected from the bit lines.

Abstract: A surface of a first aluminum interconnection layer in a connection hole is exposed to a plasma of oxygen or fluorine-containing gas during the forming step of the connection hole. In order to remove the thin deterioration layer which forms as a result, sputter etching is effected by an argon ion. There are residual particles of the oxide and fluoride of aluminum on the surface of the first aluminum interconnection layer. A titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum layer through the through hole. A titanium compound layer is formed on the titanium layer. A second aluminum layer is formed on the titanium compound layer. A heat treatment is effected to decompose the residual particles and to form an intermetallic compound (TiAl.sub.3).

Abstract: A method of forming a via structure having good characteristics in a semiconductor device having a multilayered wiring structure includes forming a thin film including a high melting point metal or a high melting point metal compound on at least the side wall of a via hole before a via plug including Al or an Al alloy is formed.

Abstract: An improved process for fabricating an integrated circuit is achieved by forming a planar conductive layer over closely spaced structures, such as gate electrode structures of field effect transistors (FET) and the electrically interconnecting word line structures of DRAM and SRAM chips. The planar conductive layer is then patterned by plasma etching to form the next level of electrical interconnecting bit lines, which makes contact to the source/drain of the FETs. The process involves the conformal deposition of a relatively thick polysilicon layer to fill the submicrometer spaces in the underlying structure. An etch back of the polysilicon and the deposition of a metal silicide is used to form an essentially planar conducting layer. This locally planar layer over submicrometer spaced features, with high aspect ratios, provides an ideal surface for exposing and developing distortion free and residue free submicrometer photoresist images required for Ultra Large Semiconductor Integration (ULSI).

Abstract: A non-aqueous electrolyte electrochemical cell comprises a negative electrode, a positive electrode, a non-aqueous electrolyte, a positive electrode case and a negative electrode case. The positive electrode case comprises a high-grade corrosion resistibility stainless steel having a pitting index between 30.5 and 45, the pitting index being calculated by the formula Cr %+3.times.Mo %+16.times.N %. An enhanced pressure sealed electrochemical cell can be manufactured in which the production cost of the positive electrode case is reduced and the productivity of the electrochemical cell improved by suppression of anodic oxidation of the positive electrode case.

Abstract: A method for cathode-side water and inert gas disposal and/or anode-side inert gas disposal from a fuel cell block having a number of fuel cells, includes increasingly concentrating a water and an inert gas component in a cathode-side gas mixture and an inert gas component in an anode-side gas mixture, in flow direction of the gas mixtures. The water and inert gas components are at least partially discharged from the fuel cell block. In an apparatus for performing the method, the fuel cells are subdivided into cell groups through which a flow of gas mixtures can be conducted in parallel. The cell groups include a cell group disposed last as seen in gas mixture flow direction. Lines connect the cell groups for conducting at least a fraction of the gas mixtures successively through the cell groups, and for discharging another fraction of the gas mixtures, being dependent on an electric current, from the fuel cell block after flowing through the last cell group.

Abstract: A metal etch processing sequence eliminates the need to use an organic masking layer solvent and etches a portion of an insulating layer after a plasma metal etching step. The etch of the insulating layer is performed with an etching solution that may include 1,2-ethanediol, hydrogen fluoride, and ammonium fluoride. The etching solution etches in a range of 100-900 angstroms of the insulating layer. The etch removes at least 75 percent of the mobile ions within the insulating layer, and should remove at least 95 percent of the mobile ions. The process may be implemented using an acid hood, an acid compatible spray tool, or a puddle processing tool. The process includes many different embodiments that allow the process to be easily integrated into many different existing processing sequences. A similar process may be used with a resist-etch-back processing sequence.

Abstract: The object of the present invention is to prevent the electrical short between the adjacent metal wires by forming metal wires alternately between insulation films and to improve the process margin in the lithography process and the etching process.The present invention alternately forms a plurality of metal wires between the insulation films by manufacturing the photomask for metal wires in two separate pieces to correspond to the photomask for general metal wires for forming a plurality of metal wires which are densely constituted, and by utilizing the two photomasks.

Abstract: A method of forming a capped and borderless contact of polysilicon on a body of a semiconductor material includes depositing a layer of undoped polysilicon on the surface of the body and forming an opening therethrough to the surface of the body. The side walls of the opening are then coated with a layer of silicon nitride and the opening is then filled with doped polysilicon which forms the contact. The doped and undoped polysilicon are heated in an oxidizing atmosphere to grow a layer of silicon dioxide thereon having a thicker portion over the doped polysilicon then over the undoped polysilicon. The silicon dioxide layer is etched to remove the thinner portion leaving the thicker portion over the doped polysilicon as a capping layer. The undoped polysilicon is then etched away and a layer of a dielectric material is deposited on the body and surrounding the doped polysilicon contact.

Abstract: This invention is directed to single phase solid solvent-containing electrolyte having recurring units derived from a diacrylate monomer having relatively rigid alkane segments within the solid polymeric matrix of such solid electrolyte as described. A preferred diacrylate monomer is 1,6-hexanediol diacrylate. Also, in a preferred embodiment recurring oxyalkylene units of 2 to 3 carbon atoms which are relatively flexible in nature are absent in the polymer backbone of the resulting solid polymeric matrix. A novel electrolytic cell that incorporates the subject electrolyte also is provided. The specific molecular structure having recurring rigid alkane groups present therein as described is believed to include relatively stable three-dimensional openings between adjacent molecular chains which advantageously facilitate the positioning of an inorganic ion salt and solvent among adjacent polymeric molecules during service within the single phase solid electrolyte.

Abstract: A method for making a tungsten plug of a semiconductor device is disclosed.The method comprises the steps of: applying an etching process to a predetermined region of an insulating film formed a conductive layer to form a contact hole, said conductive layer being exposed at the predetermined region; adding a reactive gas containing tungsten metal ions into hydrogen radical plasma to form a tungsten thin film over said insulating film and said exposed conductive layer, said tungsten thin film having a good adhesiveness to said insulating film and a very thin thickness; depositing a blanket tungsten thin film in a predetermined thickness on the resulting structure; applying an etching process to said blanket tungsten thin film and subsequently to said tungsten thin film to expose the upper surface of said insulating film.The tungsten plug formed in accordance with the present invention contains no key holes therein since the tungsten thin film is formed in a uniform thickness.

Abstract: A semiconductor connection device capable of reducing the area of connection portions by minimizing an overlapping area between a lower first conduction line and an upper second conduction line at a contact region defined in the first conduction line upon connecting the second conduction line to the first conduction line. The minimized overlapping area can be obtained by forming the second conduction line in a self-aligned manner.

Abstract: A method where WSi.sub.x films are used to contact heavily doped, n.sup.+ regions in a silicon substrate. The doped regions are formed by ion implantation of an impurity such as arsenic (As). The deposited WSi.sub.x film is annealed prior to the deposition of the aluminum interconnect. This anneal is carried out at typical dopant activation conditions. The procedure results in unexpectedly low resistance for small contact areas of less than 1.7 .mu.m.sup.2 when the WSi.sub.x film has a thickness of between 1000 .ANG. and 2500 .ANG..

Abstract: A method for forming air gaps 22 between metal leads 16 of a semiconductor device and semiconductor device for same. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16. A disposable solid layer 18 is deposited between the metal leads 16. A porous dielectric layer 20 is deposited on the disposable solid layer 18 and the tops of the leads 16, and the disposable solid layer 18 is removed through the porous dielectric layer 20, to form air gaps 22 between the metal leads 16 beneath the porous dielectric layer 20. The air gaps have a low-dielectric constant and result in reduced sidewall capacitance of the metal leads.