Abstract: A dual gate oxide semiconductor TFT substrate is made by utilizing a halftone mask to implement one photo process, which accomplishes patterning of an oxide semiconductor layer and forms an oxide conductor layer with ion doping process. Patterning of a bottom gate isolation layer and a top gate isolation layer are performed at the same time with one photo process. A first top gate, a first source, a first drain, a second top gate, a second source, and a second drain are formed at the same time with one photo process. Patterning of a flat layer, a passivation layer, and a top gate isolation layer are performed at the same time with one photo process. As such, the number of photo processes applied to manufacture the TFT substrate is reduced to five and the manufacturing process is shortened to thereby raise the production efficiency and lower the production cost.

Abstract: The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T1) and a second thin film transistor (T2) controlled by the same control signal line; the first active layer (SC1) of the first thin film transistor (T1) and the second active layer (SC2) of the second thin film transistor (T2) are at different layers, and positioned to stack up in space, and the first source (S1) and the first drain (D1) of the first thin film transistor (T1) contact the first active layer (SC1), and the second source (S2) and the second drain (D2) of the second thin film transistor (T2) contact the second active layer (SC2); the bottom gate layer (Bottom Gate) of the first thin film transistor (T1) is positioned under the first active layer (SC1), and the top gate layer (Top Gate) of the second thin film transistor (T2) is above the second active layer (SC2).

Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.

Abstract: An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Abstract: A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region and a process region, wherein the substrate support is configured to rotate the substrate; a solution container configured to hold an electroless deposition solution; a dispenser configured to provide a flow of the electroless deposition solution; a controller, the controller configured to direct the flow of the electroless deposition solution toward the edge exclusion region while the substrate is rotated, the flow being directed away from the process region, the electroless deposition solution plates metallic material over the conductive layer at the edge exclusion region, to produce an increased thickness of the metallic material that reduces electrical resistance.

Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.

Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATECNT-short-related failure mode, one metal-short-related failure mode, and one AA-short-related failure mode.

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

Abstract: A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

Abstract: Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate, and a vertical source/drain contact. The vertical FET device comprises a first source/drain region disposed on a buried insulating layer of the substrate. The first source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface that contacts the buried insulating layer. The vertical source/drain contact is disposed adjacent to the vertical FET device and contacts at least one sidewall surface of the first source/drain region. The vertical source/drain contact comprises an extended portion which is disposed between the first source/drain region and the buried insulating layer and in contact with at least a portion of the bottom surface of the first source/drain region.

Abstract: A semiconductor light emitting device includes a substrate formed of a first material; and a convex portion protruding from the substrate and including: a first layer formed of the first material as that of the substrate; and a second layer formed of a second material different from the first material and disposed on the first layer. A second height of the second layer is greater than a first height of the first layer.

Abstract: A first electrode having light transmissivity is formed on a first surface of a first light transmissive substrate and. An organic functional layer includes a light-emitting layer and is located on an opposite side to the first light transmissive substrate with the first electrode interposed therebetween. A second electrode is located on an opposite side to the first electrode with the organic functional layer interposed therebetween. A second surface which is a surface of the first light transmissive substrate on an opposite side to the above-mentioned first surface is fixed to the second light transmissive substrate, which has a bending rigidity higher than that of the first light transmissive substrate. First irregularities are formed in the second surface of the first light transmissive substrate, and second irregularities are formed in a surface of the second light transmissive substrate which faces the first light transmissive substrate.

Abstract: Disclosed is a method for manufacturing a TFT substrate, which uses one partial transmitting mask to form patterns of an active layer, a gate insulation layer, and a gate electrode through photolithography such that the entire process for manufacturing TFT substrate can be completely conducted by using only three masks. Compared to the prior art, one mask is save so that the operation is simplified and the manufacturing cost is reduced.

Abstract: The present invention provides a frameless display device and a manufacturing method thereof, in which a conductive connection body is formed on a substrate; a first via is formed in a protective layer to be located above the conductive connection body and a second via hole is formed in the substrate to be located under the conductive connection body. A circuit layout layer is connected through the first via with the conductive connection body and a flexible connection circuit connected to a drive circuit board is connected through the second via with the conductive connection body thereby achieving electrical connection between the drive circuit board and the circuit layout layer. The method is simple and easy to operate and in a frameless display device so manufactured, the flexible connection circuit and the drive circuit board are both arranged at a back side of the substrate without occupying an effective display zone thereby achieving frameless displaying and improving displaying quality.

Abstract: A display device includes a plurality of pixels on a substrate including an insulating surface. Each of the plurality of pixels includes: a transistor above the insulating surface; a planarization film covering the transistor; a pixel electrode above the planarization film and electrically connected with the transistor; an insulating layer filled in a recess located around the pixel electrode between the pixels adjacent to each other; a light-emitting layer covering a surface of the pixel electrode and at least a part of a surface of the insulating layer; and a counter electrode above the light-emitting layer. A distance between a surface of the substrate and a face of the light-emitting layer in contact with the insulating layer is equal to or smaller than a distance between the surface of the substrate and a face of the light-emitting layer in contact with the pixel electrode.

Abstract: A thin film transistor (TFT) substrate includes a substrate and a TFT. The TFT is disposed on the substrate and comprises a gate, a gate dielectric layer, a film, a source and a drain. The gate is disposed on the substrate. The gate dielectric layer is disposed on the gate and the substrate. The film is disposed above the gate dielectric layer, and the source and the drain are disposed on the film and contacts with the film respectively. Wherein, there is an interval between the source and the drain, and the film corresponding to the interval has an arc concave portion. In addition, a display panel is also disclosed.

Abstract: A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device comprises a process of forming a metal layer on an N surface of a nitride semiconductor substrate. The process of forming the metal layer includes a first process of forming a metal layer by sputtering at a film formation rate controlled to 4 nm/minute or lower.

Abstract: Photonic integrated circuits (PICs) are based on quantum cascade (QC) structures. In embodiment methods and corresponding devices, a QC layer in a wave confinement region of an integrated multi-layer semiconductor structure capable of producing optical gain is depleted of free charge carriers to create a low-loss optical wave confinement region in a portion of the structure. Ion implantation may be used to create energetically deep trap levels to trap free charge carriers. Other embodiments include modifying a region of a passive, depleted QC structure to produce an active region capable of optical gain. Gain or loss may also be modified by partially depleting or enhancing free charge carrier density. QC lasers and amplifiers may be integrated monolithically with each other or with passive waveguides and other passive devices in a self-aligned manner. Embodiments overcome challenges of high cost, complex fabrication, and coupling loss involved with material re-growth methods.