Abstract: A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.

Abstract: A RRAM device having a diode device structure coupled to a variable resistance layer is disclosed. The diode device structure can either be embedded into or fabricated over the substrate. A memory device having an array of said RRAM devices can be fabricated with multiple common bit lines and common word lines.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.

Abstract: Disclosed are a method of manufacturing a flexible thin-film type super-capacitor device and a super-capacitor device manufactured by the same. The flexible thin-film type super-capacitor device comprises a base film which has flexibility; a separator which is interposed between the base films; and an active material which is formed on the base film. Thus, flexibility is given since thickness is very thin while maintaining high electrical conductivity and high binding property. In addition, economic feasibility is high and mass production is possible. Further, it is possible to stably and efficiently contain a highly corrosive material.

Abstract: Semiconductor devices are provided which comprise III-V FINFET devices that are formed with different semiconductor fin widths to obtain different threshold voltages, as well as methods for fabricating such III-V FINFET devices. For example, a semiconductor device comprises first and second semiconductor fins, which are formed of a III-V compound semiconductor material, and which have a first width W1 and a second width W2, respectively, wherein W1 is less than W2. First and second gate structures of first and second FINFET devices are formed over a portion of the first and second semiconductor fins, respectively. The first FINFET device comprises a first threshold voltage and the second FINFET device comprises a second threshold voltage. The first threshold voltage is greater than the second threshold voltage as a result of the first width W1 being less than the second width W2.

Abstract: A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

Abstract: A manufacturing method of a MEMS sensor includes forming a first substrate, wherein the first substrate includes a lower electrode provided at one surface thereof, forming a second substrate, wherein the second substrate includes a first concave-convex portion provided at one surface thereof, first-bonding one surface of the first substrate and one surface of the second substrate to face each other, forming a third substrate, wherein the third substrate includes an upper electrode provided at one surface thereof, second-bonding another surface of the second substrate and one surface of the third substrate to face each other, and forming an electrode line on another surface of the third substrate to be connected to the lower electrode and the upper electrode.

Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

Abstract: A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode. Radiofrequency power is supplied to the electrode to generate a plasma within the plasma generation region during multiple sequential plasma processing cycles of a plasma processing operation. At least one electrical sensor connected to the electrode measures a radiofrequency parameter on the electrode during each of the multiple sequential plasma processing cycles. A value of the radiofrequency parameter as measured on the electrode is determined for each of the multiple sequential plasma processing cycles. A determination is made as to whether or not any indicatory trend or change exists in the values of the radiofrequency parameter as measured on the electrode over the multiple sequential plasma processing cycles, where the indicatory trend or change indicates formation of a plasma instability during the plasma processing operation.

Abstract: There is provided a method of filling a recess with a germanium-based film composed of germanium or silicon germanium in a substrate to be processed on which an insulating film having the recess formed therein is formed, the method including: forming a silicon film on a surface of the insulating film at a thickness as not to completely fill the recess; subsequently, etching the silicon film such that the silicon film remains only in a bottom portion of the recess; and subsequently, selectively growing the germanium-based film composed of germanium or silicon germanium on the silicon film remaining in the bottom portion of the recess and selectively filling the recess with the germanium-based film.

Abstract: A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active layer, a source-drain metal layer and a diffusion blocking layer located between the active layer and the source-drain metal layer, wherein, the source-drain metal layer includes a source electrode and a drain electrode; the diffusion blocking layer includes a source blocking part corresponding to a position of the source electrode and a drain blocking part corresponding to a position of the drain electrode; and the diffusion blocking layer is doped with different concentrations of nitrogen from a side close to the source-drain metal layer to a side close to the active layer.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes forming an anode on a substrate, forming a lift-off layer on the substrate including the anode, the lift-off layer including a fluoropolymer, forming a polymer layer on the lift-off layer, forming a pattern on a first portion of the polymer layer overlapping the anode using a roll-to-roll stamp process, etching a first portion of the lift-off layer corresponding to the pattern using a first solvent including fluorine, the first portion of the lift-off layer being disposed on the anode, forming an organic functional layer including a light-emitting layer on the anode and a second portion of the polymer layer not formed with the pattern, removing the lift-off layer using a second solvent including fluorine, and forming a cathode on the organic functional layer.

Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.

Abstract: In various embodiments, evaporation sources are heated and/or cooled via a fluid-based thermal management system during deposition of thin films.

Abstract: A molded sensor package includes a leadframe having a sensor die attached to the leadframe, a magnet aligned with the sensor die and a single molding compound encasing the sensor die and attaching the magnet to the leadframe. A method of manufacturing the molded sensor package includes loading the magnet and the leadframe into a molding tool so that the magnet is aligned with the sensor die in the molding tool, molding the magnet and the sensor die with the same molding compound while loaded in the molding tool and curing the molding compound so that the magnet is attached to the leadframe by the same molding compound that encases the sensor die.

Abstract: The present invention discloses a TFT substrate and a display device. The TFT substrate comprises a scan line, a data line and a common electrode covering the scan line and the data line, wherein the data line and the scan line are disposed in a stagger, in order to divide the crosswise formed region into a plurality of pixel units; the common electrode comprises a plurality of common electrode units and a plurality of bridging portions overlapping with the scan lines and the data lines, wherein the common electrode unit and the pixel unit are correspondingly disposed, each bridging portion is connected with at least two adjacent common electrodes in order to make all of the common electrodes be electrically connected. Through the above ways, the present invention can reduce the RC constant and power consumption, thereby improving the product quality.

Abstract: Disclosed herein is a wafer processing method including a cover plate providing step of providing a cover plate on the front side of a wafer to thereby form a composite wafer, a welding step of applying a laser beam along each division line formed on the front side of the wafer in the condition where the focal point of the laser beam is set at the interface between the wafer and the cover plate on opposite sides of the lateral center of each division line, thereby forming two parallel welded lines for joining the wafer and the cover plate along each division line, and a dividing step of forming a cut line between the two parallel welded lines formed along each division line, thereby cutting the composite wafer along each division line to obtain individual device chips each covered with the cover plate.

Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

Abstract: The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode pattern and a data line pattern located on the active layer pattern included in the array substrate. A surface of the array substrate includes a first region corresponding to the source electrode pattern, the drain electrode pattern and the data line pattern, a second region corresponding to a region of the active layer pattern located between the source electrode pattern and the drain electrode pattern, as well as a third region in addition to the first region and the second region; the half tone mask plate includes a semi-transparent region corresponding to the second region and a partial region of the third region.

Abstract: A pixel array including an SixGey layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the SixGey layer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the SixGey layer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the SixGey layer.