Patents Examined by Caleb Henry
  • Method of manufacturing nitride semiconductor device using laminated cap layers
    Patent number: 9805930
    Abstract: A method of manufacturing a nitride semiconductor device is provided, comprising: forming, on a substrate, a first laminated body where a first nitride semiconductor layer, a second nitride semiconductor layer and a third nitride semiconductor layer are laminated in this order; subsequent to the forming, removing a partial region of the third nitride semiconductor layer, subsequent to the removing; implanting ions to the first nitride semiconductor layer from the partial region where the third nitride semiconductor layer is removed at least through the second nitride semiconductor layer; and subsequent to the implanting the ions, annealing the first laminated body.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 31, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryo Tanaka, Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Fluorinated organic electroluminescent materials and devices
    Patent number: 9799838
    Abstract: Novel ligands for metal complex compounds that are useful as a phosphorescent emitter in organic light emitting devices that incorporate fluorinated side chains in the ligands are disclosed. Such metal complex has at least one substituent R selected from the group consisting of partially fluorinated alkyl, partially fluorinated cycloalkyl, and combinations thereof, wherein R is directly bonded to an aromatic ring, In the compound, C having an F attached thereto is separated by at least one carbon atom from the aromatic ring.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 24, 2017
    Assignee: Universal Display Corporation
    Inventors: Pierre-Luc T. Boudreault, Walter Yeager, Chuanjun Xia
  • Structure of dual gate oxide semiconductor TFT substrate
    Patent number: 9799677
    Abstract: A dual gate oxide semiconductor thin-film transistor (TFT) substrate includes a substrate; a bottom gate positioned on the substrate; a bottom gate isolation layer positioned on the substrate and the bottom gate; a first oxide semiconductor layer positioned on the bottom gate isolation layer above the bottom gate; an oxide conductor layer positioned on the bottom gate isolation layer at one side of the first oxide semiconductor layer; a top gate isolation layer positioned on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate isolation layer; a top gate positioned on the top gate isolation layer above a middle part of the first oxide semiconductor layer; a source and a drain positioned on the top gate isolation layer at two sides of the top gate; and a passivation layer positioned on the top gate isolation layer, the source, the drain, and the top gate.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: October 24, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shimin Ge, Hejing Zhang, Chihyuan Tseng, Chihyu Su, Wenhui Li, Longqiang Shi, Xiaowen Lv
  • Inductor heat dissipation in an integrated circuit
    Patent number: 9799720
    Abstract: The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Organic material deposition apparatus, and organic material deposition method using same
    Patent number: 9797038
    Abstract: An apparatus for depositing an organic material includes: a main chamber; a first substrate loading section in which a first substrate is loaded in the first radial direction and seated; a second substrate loading section in which a second substrate is loaded in the second radial direction and seated; a scanner including a linear organic material deposition source, a source moving means to which the organic material deposition source is coupled to linearly move the organic material deposition source so that the organic material particles are injected onto the surface of the first substrate or the second substrate, and a rotating means for rotating the source moving means; and a scanner moving means for moving the scanner back and forth so that the scanner is positioned in the first deposition region or the second deposition region.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 24, 2017
    Assignee: SUNIC SYSTEMS, LTD.
    Inventors: Chang Sik Choi, Young Im, Young Jong Lee, Seong Ho Kim, Sun Hyuk Kim, Jung Gyun Lee, In Ho Hwang
  • Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
    Patent number: 9786649
    Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 10, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
    Patent number: 9786650
    Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 10, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Isolation structure of semiconductor device
    Patent number: 9786543
    Abstract: The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Han Chen, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Manufacturing method and manufacturing apparatus of liquid crystal display device
    Patent number: 9785014
    Abstract: In a photo alignment process according to a manufacturing method of a liquid crystal display device including a display panel with a liquid crystal layer interposed between substrates, in order to even the exposure amount of ultraviolet light in an area of a substrate passing through the lower central portion of a bar-like UV lamp arranged in a prolonged way in a direction crossing the proceeding direction of the substrate and in an area of the substrate passing through the end portions thereof, the ultraviolet light is irradiated through an aperture having a larger opening width in the end portions than in the center portion.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 10, 2017
    Assignee: Japan Display Inc.
    Inventor: Yojiro Shimada
  • Integrated circuit packages and methods for forming the same
    Patent number: 9780009
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Seal rings structures in semiconductor device interconnect layers and methods of forming the same
    Patent number: 9780046
    Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Pan, Han-Ping Pu, Pei-Haw Tsao, Yu-Chen Hsu
  • Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
    Patent number: 9778974
    Abstract: An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 3, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Method for manufacturing mixed-dimension and void-free MRAM structure
    Patent number: 9780301
    Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Jiunyu Tsai, Hung Cho Wang, Tsun Chung Tu
  • Method of fabricating a semiconductor structure
    Patent number: 9779963
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
  • Method of fabricating 3D NAND
    Patent number: 9779948
    Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: October 3, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Baraskar, Yanli Zhang, Ching-Huang Lu, Zhenyu Lu
  • Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells
    Patent number: 9773773
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one GATECNT-short-related failure mode.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 26, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
    Patent number: 9773775
    Abstract: An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of snake opens.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 26, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Semiconductor die singulation method using varied carrier substrate temperature
    Patent number: 9773689
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. A support structure is used to heat and/or cool at least the first carrier-substrate while the localized pressure is applied.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: September 26, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Lithography using high selectivity spacers for pitch reduction
    Patent number: 9773676
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Cross-point memory and methods for fabrication of same
    Patent number: 9768378
    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Andrea Ghetti