Abstract: An antireflective coating composition, including a polymer, a photoacid generator having a crosslinkable group, a compound capable of crosslinking the polymer and the photoacid generator, a thermal acid generator, and an organic solvent.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.

Abstract: Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a photo-sensitive layer on a first surface of a semiconductor substrate. The photo-sensitive layer has a top surface. The method also includes obtaining a first profile of the first surface of the semiconductor substrate, and obtaining a second profile of the top surface of the photo-sensitive layer. The method also includes calculating a vertical displacement profile of the semiconductor substrate according to the first profile and the second profile. An apparatus for manufacturing a semiconductor structure is also disclosed.

Abstract: A mask plate, a method for manufacturing a patterned film layer and a manufacturing method of a thin film transistor are provided by the embodiments of the present disclosure. The mask plate includes: a first pattern and a second pattern; the first pattern includes a first sidewall, a second sidewall, a connecting portion connecting the first sidewall and the second sidewall, and an extension portion on a side of the connecting portion away from the first sidewall; the second pattern is between the first sidewall and the second sidewall; a slit is between the first pattern and the second pattern, and the slit is configured for diffraction. The positive photoresist is used, the extension portion of the mask plate makes that the pattern of the photoresist formed by the mask plate with the extension portion has a region corresponding to the extension portion and the “bolt effect” is avoided.

Abstract: A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a polymer that includes a substituted biphenylene structural unit, wherein one phenylene of the biphenylene of the substituted biphenylene structural unit is substituted with at least one of a hydroxy-substituted C6 to C30 aryl group, and a hydroxy-substituted C3 to C30 heteroaryl group.

Abstract: A photoresist composition comprises a polymer resin, a photoactive compound, an organometallic compound, an enhancement additive, and a first solvent. The enhancement additive is an ionic surfactant, a non-ionic surfactant, or a second solvent having a boiling point of greater than 150° C.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The source structure includes a plurality of source contacts, and two adjacent ones of the plurality of source contacts are conductively connected to one another by a connection layer. A pair of first portions of the connection layer are over the two adjacent ones of the plurality of source contacts and a second portion of the connection layer being between the two adjacent ones of the plurality of source contacts. Top surfaces of the pair of first portions of the connection are coplanar with a top surface of the second portion.

Abstract: Disclosed are a polymer including a structural unit represented by Chemical Formula 1 and a structural unit represented by Chemical Formula 2, an organic layer composition including the polymer, and a method of forming patterns using the organic layer composition. The Chemical Formulae 1 and 2 are the same as defined in the specification.

Abstract: A chemically amplified resist composition comprising a quencher containing an ammonium salt of an iodized or brominated aromatic ring-bearing carboxylic acid, and an acid generator exhibits a sensitizing effect and an acid diffusion suppressing effect and forms a pattern having improved resolution, LWR and CDU.

Abstract: An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.

Abstract: Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer.

Abstract: An interconnect or memory structure is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A first metal-containing cap contacts the concave upper surface of the first electrically conductive structure. The first metal-containing cap has a topmost surface that is coplanar with a topmost surface of the first interconnect dielectric material layer. A second metal-containing cap having a planar bottommost surface contacts the topmost surface of the first metal-containing cap. A metal-containing structure having a planar bottommost surface contacts a planar topmost surface of the second metal-containing cap.

Abstract: According to one embodiment, a pattern forming material is disclosed. The pattern forming material contains a polymer. The polymer includes a specific first monomer unit. The monomer unit has a structure having ester of a carboxyl group at a terminal of a side chain. In the ester, a carbon atom bonded to an oxygen atom next to a carbonyl group is a primary carbon, a secondary carbon or a tertiary carbon. The pattern forming material is used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film is formed by a process including, forming an organic film on the target film with the pattern forming material, patterning the organic film, and forming the composite film by infiltering a metal compound into the patterned organic film.

Abstract: A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate.

Abstract: An adhesive can be easily peeled off after polishing the back face of a wafer, which has heat resistance and can be easily washed off. An adhesive for peelably adhering between a support and a circuit-bearing face of a wafer and thereby processing a back face of the wafer, a peeling face upon peeling becomes selectable according to heating from the support side or wafer side when the adhesive is cured. The adhesive includes a component (A) curing by hydrosilylation reaction and a component (B) containing a polydimethylsiloxane. A peeling method including forming an adhesion layer by applying the adhesive to a surface of a first substrate, bonding a surface of a second substrate to the adhesion layer, curing the adhesion layer by heating from the first substrate side to form a laminate, processing the laminate, and peeling off between the first substrate and the adhesion layer.

Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a wafer having a functional region and a non-functional region surrounding the functional region; forming a first dielectric layer on the wafer; forming a first opening in the first dielectric layer in the non-functional region; and forming a first connection layer in the first opening. The first connection layer closes a top portion of the first opening, and a void is formed in the first connection layer in first opening.