Patents Examined by Caleen O. Sullivan
  • Patent number: 11169441
    Abstract: A resist underlayer film forming composition characterized by containing (A) a compound represented by formula (1) (in formula (1), independently, R1 represents a C1 to C30 divalent group; each of R2 to R7 represents a C1 to C10 linear, branched, or cyclic alkyl group, a C6 to C10 aryl group, a C2 to C10 alkenyl group, a thiol group, or a hydroxyl group; at least one R5 is a hydroxyl group or a thiol group; each of m2, m3, and m6 is an integer of 0 to 9; each of m4 and m7 is an integer of 0 to 8; m5 is an integer of 1 to 9; n is an integer of 0 to 4; and each of p2 to p7 is an integer of 0 to 2) and a cross-linkable compound represented by formula (2-1) or (2-2) (in formula (2), Q1 represents a single bond or an m12-valent organic group; each of R12 and R15 independently represents a C2 to C10 alkyl group or a C2 to C10 alkyl group having a C1 to C10 alkoxy group; each of R13 and R16 represents a hydrogen atom or a methyl group; each of R14 and R17 represents a C1 to C10 alkyl group or a C6 to C40 aryl group;
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 9, 2021
    Assignee: NISSAN CHEMICAL CORPORATION
    Inventors: Daigo Saito, Keisuke Hashimoto, Rikimaru Sakamoto
  • Patent number: 11164965
    Abstract: A semiconductor device of an embodiment includes first and second electrodes; first and second gate electrodes; and semiconductor layer including first and second planes, the semiconductor layer including a first semiconductor region of first conductivity type including first portion, second portion having a carrier concentration higher than the first portion, and third portion having a carrier concentration lower than the second portion; a second semiconductor region of second conductivity type between the first semiconductor region and the first plane and facing the first gate electrode; a third semiconductor region of first conductivity type between the second semiconductor region and the first plane and contacting the first electrode; a fourth semiconductor region of second conductivity type between the first semiconductor region and the second plane and facing the second gate electrode; and a fifth semiconductor region of first conductivity type between the fourth semiconductor region and the second plan
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 2, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Takeshi Suwa
  • Patent number: 11164767
    Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: November 2, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Hua Chung, Schubert S. Chu
  • Patent number: 11158630
    Abstract: A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p+ type diffusion layer and an n+ type source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the n+ type source layer and the p+ type diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the p+ type diffusion layer is interposed between the p type channel doped layer and an n+ type source layer, and the p type channel doped layer and the n+ type source layer are not adjacent to each other.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: October 26, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Mitsuru Kaneda
  • Patent number: 11152253
    Abstract: A semiconductor structure and a method of fabricating the same is disclosed. The structure comprises: a substrate having a device region; a contact plug arranged over the device region and enables electrical connection to a semiconductor device in the device region; a separation layer arranged above and exposing the contact plug; a cylindrical tubular metal feature arranged above the separation layer; and a dielectric layer laterally surrounding the cylindrical tubular conductive feature, having a substantially stepped dopant concentration distribution comprised of two distinct dopant species. The dopant concentration level decreases from a lower region nearest the separation layer toward an upper region farther from the separation layer. An inter-dopant ratio between the distinct dopant species increases from the lower region toward the upper region. The cylindrical tubular metal feature has a sidewall profile that is substantially perpendicular to a surface of the substrate.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 19, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Jee-Hoon Kim, Hyunyoung Kim, Kang-Won Seo
  • Patent number: 11145560
    Abstract: A photoresist with a detection additive is utilized to help increase the contrast of images during an after development inspection process. The detection additive fluoresces during the after development inspection process and adds to the energy that is reflected during the after development inspection process, increasing the contrast during the after development inspection process and helping to identify defects that are not otherwise detectable.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hsing-Chieh Lee, Ming-Tan Lee
  • Patent number: 11126084
    Abstract: A composition for resist underlayer film formation contains a compound having a group represented by formula (1), and a solvent. R1 represents an organic group having 2 to 10 carbon atoms and having a valency of (m+n), wherein the carbon atoms include two carbon atoms that are adjacent to each other, with a hydroxy group or an alkoxy group bonding to one of the two carbon atoms, and with a hydrogen atom bonding to another of the two carbon atoms; L1 represents an ethynediyl group or a substituted or unsubstituted ethenediyl group; R2 represents a hydrogen atom or a monovalent organic group having 1 to 20 carbon atoms; n is an integer of 1 to 3; * denotes a bonding site to a moiety other than the group represented by the formula (1) in the compound; and m is an integer of 1 to 3.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 21, 2021
    Assignee: JSR CORPORATION
    Inventors: Naoya Nosaka, Goji Wakamatsu, Tsubasa Abe, Yuushi Matsumura, Yoshio Takimoto, Shin-ya Nakafuji, Kazunori Sakai
  • Patent number: 11121090
    Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changbo Lee, Joonseok Oh, Byunglyul Park
  • Patent number: 11112695
    Abstract: Provided are a photosensitive composition with which a cured film having excellent heat resistance and pattern formability can be formed, a cured film, an optical filter, a solid image pickup element, an image display device, and an infrared sensor. This photosensitive composition includes an infrared shielding agent A, a polymer component B, and a photoacid generator C. The polymer component B in the photosensitive composition includes, for example, a polymer B1 that includes a repeating unit b1 having a group in which at least one group selected from an acid group or a hydroxyl group is protected by an acid-decomposable group and a repeating unit b2 having a crosslinking group.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 7, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Kyohei Arayama
  • Patent number: 11106126
    Abstract: In a method of manufacturing a photo mask, an etching mask layer having circuit patterns is formed over a target layer of the photo mask to be etched. The photo mask includes a backside conductive layer. The target layer is etched by plasma etching, while preventing active species of plasma from attacking the backside conductive layer.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chang Lee, Pei-Cheng Hsu, Ta-Cheng Lien, Tzu Yi Wang
  • Patent number: 11101240
    Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11094852
    Abstract: Light emitting diode (LED) packages and LED displays utilizing the LED packages are disclosed. LED packages can have a plurality of cavities with each having one or more LEDs. The LEDs can be individually controllable so that the LED package emits the desired color combination of light from the package. The LED packages are arranged with an encapsulant over the cavities that shape the LED package emission to a wide angle or pitch. Some of the LED packages can have three cavities, while others can have four or more cavities. The packages can comprise an encapsulant that forms lenses over the cavities and continues beyond the cavities to cover surfaces of the LED package body. The body can include different anchoring features to improve package reliability by anchoring the encapsulant to the body. One embodiment of an LED display according to the present invention comprises a plurality of LED packages, at least some having a plurality of cavities.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 17, 2021
    Assignee: Cree Huizhou Solid State Lighting Company Limited
    Inventors: Chak Hau Charles Pang, Yue Kwong Victor Lau, JuZuo Sheng, Christopher P. Hussell
  • Patent number: 11094867
    Abstract: A display device and a method of manufacturing the same are provided. A display device includes: a substrate, a pixel circuit on the substrate, the pixel circuit including: a gate electrode, a drain electrode, and a source electrode, a vertical LED element on the substrate, the vertical LED element including: a first electrode, an active layer under the first electrode, and a second electrode under the active layer, an encapsulation film surrounding the vertical LED element, the encapsulation film exposing a portion of a side of the second electrode, a first connection electrode electrically connected to the first electrode, and a second connection electrode electrically connected to the second electrode.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 17, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: HanSaem Kang
  • Patent number: 11088196
    Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Yimin Huang
  • Patent number: 11079677
    Abstract: An object of the present invention is to provide a chemical liquid which makes it difficult for a defect to occur on a substrate after development. Another object of the present invention is to provide a chemical liquid storage body and a pattern forming method. The chemical liquid of the according to an embodiment of the present invention contains a main agent which is formed of one kind of organic solvent or formed of a mixture of two or more kinds of organic solvents, an impurity metal, and a surfactant, in which a vapor pressure of the main agent is 60 to 1,340 Pa at 25° C., the impurity metal contains particles containing one kind of metal selected from the group consisting of Fe, Cr, Ni, and Pb, in a case where the chemical liquid contains one kind of particles, a content of the particles in the chemical liquid is 0.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 3, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuya Kamimura
  • Patent number: 11079676
    Abstract: A radiation-sensitive composition is to be used in exposure with an extreme ultraviolet ray or an electron beam, and includes a first polymer and a solvent, wherein the first polymer includes a first structural unit including: at least one metal atom; and at least one carbon atom that each bonds to the metal atom by a chemical bond and does not constitute an unsaturated bond, and at least one chemical bond is a covalent bond. Every chemical bond is preferably a covalent bond. The metal atom is preferably tin, germanium, lead or a combination thereof.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 3, 2021
    Assignee: JSR CORPORATION
    Inventors: Yusuke Asano, Hisashi Nakagawa, Shinya Minegishi
  • Patent number: 11073762
    Abstract: Provided are an actinic ray-sensitive or radiation-sensitive resin composition which contains (A) a photoacid generator that generates an acid having a pKa of ?1.40 or more upon irradiation with actinic rays or radiation, and (B) a resin having a repeating unit containing an acid-decomposable group, in which an Eth sensitivity of the repeating unit containing an acid-decomposable group is 5.64 or less, and which can provide very excellent roughness performance, exposure latitude, and depth of focus, particularly, in the formation of an ultrafine pattern; a photoacid generator; and an actinic ray-sensitive or radiation-sensitive film, a pattern forming method, and a method for manufacturing an electronic device, each using the actinic ray-sensitive or radiation-sensitive resin composition.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: July 27, 2021
    Assignee: FUJIFILM Corporation
    Inventors: Daisuke Asakawa, Akiyoshi Goto, Masafumi Kojima, Keita Kato, Keiyu Ou, Kyohei Sakita
  • Patent number: 11075111
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Hoon Kim
  • Patent number: 11069815
    Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Auburn University
    Inventors: Minseo Park, Michael C. Hamilton, Shiqiang Wang, Kosala Yapa Bandara
  • Patent number: 11063078
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. A first side of an optically transmissive lid may be coupled to the second side of the semiconductor die through one or more dams. The packages may also include a light block material around the semiconductor package extending from the first side of the semiconductor die to a second side of the optically transmissive lid. The package may include an opening in the light block material on the second side of the optically transmissive lid that substantially corresponds with an active area of the semiconductor die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 13, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Shou-Chian Hsu