Patents Examined by Calvin Choi
  • Patent number: 10177096
    Abstract: Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Gug Min, Sungil Cho, Jaehoon Choi, Shi-kyung Kim
  • Patent number: 10163765
    Abstract: A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiko Happoya
  • Patent number: 10163922
    Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichiro Abe, Masaaki Shinohara
  • Patent number: 10158028
    Abstract: Provided is a semiconductor device including a substrate having a first conductivity type, a first well having a second conductivity type, a first doped region having the first conductivity type, a second well having the second conductivity type, at least one second doped region having the first conductivity type, at least one third doped region having the second conductivity type, and a fourth doped region having the second conductivity type. The first well is located in the substrate. The first doped region is located in the first well. The second well is located in the first well. The second doped region is located in the first doped region. The third doped region is located in the first well at a first side of the first doped region. The fourth doped region is located in the first well at a second side of the first doped region.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 18, 2018
    Assignee: MACROIX International Co., Ltd.
    Inventor: Ying-Chieh Tsai
  • Patent number: 10147599
    Abstract: Methods for the formation of SiCN, SiCO and SiCON films comprising cyclical exposure of a substrate surface to a silicon-containing gas, a carbon-containing gas and a plasma. Some embodiments further comprise the addition of an oxidizing agent prior to at least the plasma exposure.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: December 4, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ning Li, Mark Saly, David Thompson, Mihaela Balseanu, Li-Qun Xia
  • Patent number: 10141392
    Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic capacitor plate structure embedded therein, wherein each metallic capacitor plate structure has a columnar grain microstructure. A high-k dielectric material is present between the first and second metallic capacitor plate structures. The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10141391
    Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic pad structure embedded therein, wherein each metallic pad structure has a columnar grain microstructure. A metal resistor structure is embedded in one of the first bonding oxide layer or the second bonding oxide and is present between the first and second metallic pad structures.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10134684
    Abstract: A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned shield structure includes a center structure unit, a first patterned structure unit, and a second patterned structure unit. The center structure unit includes a first sub-center structure unit and a second sub-center structure unit. The second sub-center structure unit and the first sub-center structure unit are symmetrically disposed with respect to a middle of the center structure unit. The first patterned structure unit is disposed on one side of the center structure unit. The second patterned structure unit is disposed on another side of the center structure unit. The second patterned structure unit and the first patterned structure unit are symmetrically disposed with respect to the center structure unit.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: November 20, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10128173
    Abstract: In some examples, a device includes an input leadframe segment and a reference leadframe segment that is electrically isolated from the input leadframe segment. The device further includes at least four transistors comprising at least two high-side transistors that are electrically connected to the input leadframe segment and at least two low-side transistors that are electrically connected to the reference leadframe segment. The device further includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors, each switching element of the at least two switching elements is electrically connected to a respective low-side transistor of the at least two low-side transistors, and the at least four transistors include at least one discrete transistor.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10126610
    Abstract: The present disclosure provides an array substrate, manufacturing method thereof and a display device. A method of manufacturing an array substrate includes: sequentially forming a common electrode line, a first insulating layer, a pixel electrode, and a second insulating layer, and forming a via that is in communication with the common electrode line. The method further comprises, after forming the via, forming a common electrode that covers the via through a patterning process, wherein the patterning process includes etching a portion of the via covered with the common electrode to form an isolated region. The isolated region includes a region at an inner side of a first edge of the via. The first edge is an edge of the via adjacent to or stacked with the pixel electrode. The via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Pijian Jia, Zhaohui Hao, Lin Li, Lingqi Meng, Huzhao Shi
  • Patent number: 10121722
    Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Chandra M. Jha, Eric J. Li, Zhaozhi Li, Robert M. Nickerson
  • Patent number: 10121792
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 10096559
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byoung Chan Kim, Yong Ho Baek
  • Patent number: 10096560
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byoung Chan Kim, Yong Ho Baek
  • Patent number: 10081868
    Abstract: Provided is a technology including a nozzle base end portion which is provided in a processing chamber processing a substrate to extend in a vertical direction and into which a processing gas processing the substrate is introduced, a nozzle distal end portion which is configured in a U shape and in which a gas supply hole supplying the processing gas is provided to a side surface of the substrate, and a gas residence suppressing hole which is provided in a downstream end of the nozzle distal end portion and has a diameter larger than that of the gas supply hole.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 25, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kosuke Takagi, Ryota Sasajima, Shintaro Kogura, Naonori Akae, Risa Yamakoshi, Toshiki Fujino, Masato Terasaki, Masayoshi Minami
  • Patent number: 10079112
    Abstract: A method for producing an electrolytic capacitor is performed in the following procedure. A solid electrolyte layer including a conductive polymer and a polyhydric alcohol is formed on an anode body on which a dielectric layer is formed. Then, the anode body on which the solid electrolyte layer is formed is impregnated with a first treatment liquid that contains an oxoacid having two or more hydroxy groups.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: September 18, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yuichiro Tsubaki, Masahiro Kajimura
  • Patent number: 10074533
    Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 ?m and a height between 1 and 500 ?m.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 11, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Chun Yeh, Kan-Hsueh Tsai, Chuan-Wei Tsou, Heng-Yuan Lee, Hsueh-Hsing Liu, Han-Chieh Ho, Yi-Keng Fu
  • Patent number: 10069017
    Abstract: A diode includes an n type semiconductor layer including an n type cathode layer and an n type drift layer that has an impurity concentration lower than the n type cathode layer and that is disposed on the n type cathode layer, a p type anode layer disposed at a surface part of the n type drift layer, a p type hole implantation layer selectively disposed at the n type cathode layer, an anode electrode electrically connected to the p type anode layer, and a cathode electrode electrically connected to the n type cathode layer and to the p type hole implantation layer, and the p type hole implantation layer has a diameter of 20 ?m or more.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: September 4, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Shinya Umeki
  • Patent number: 10050007
    Abstract: An electronic device includes: a substrate having an upper surface (front surface) on which a semiconductor chip is mounted, and a lower surface (back surface) opposite to the upper surface; and a housing (case) fixed to the substrate through an adhesive material. The housing has through-holes each formed on one short side and the other short side in an X direction. The substrate is disposed between the through-holes. A part of the upper surface of the substrate is fixed so as to face a part of a stepped surface formed at a height different from that of a lower surface of the housing. Further, an interval (distance) between a part (stepped surface) extending along a short side of the housing in the stepped surface and the upper surface of the substrate is larger than an interval (distance) between a part (stepped surface) extending along a long side of the housing in the stepped surface and the upper surface of the substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Bando
  • Patent number: 10050003
    Abstract: A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 14, 2018
    Assignee: eSilicon Corporation
    Inventor: Javier DeLaCruz