Abstract: A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range.

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Abstract: The present invention provides a MEMS and a sensor having the MEMS which can be formed without a process of etching a sacrifice layer. The MEMS and the sensor having the MEMS are formed by forming an interspace using a spacer layer. In the MEMS in which an interspace is formed using a spacer layer, a process for forming a sacrifice layer and an etching process of the sacrifice layer are not required. As a result, there is no restriction on the etching time, and thus the yield can be improved.

Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

Abstract: A method that includes obtaining, using a processor, reflectance data from a target coating and calculating, using the processor, virtual color response data using one of at least one Kepler's laws of planetary motion equation and at least one derivation of at least one Kepler's laws of planetary motion equation. The method also includes generating, using the processor, a coating formulation that is the same or substantially similar in appearance to the target coating.

Abstract: A semiconductor switch includes an insulating film on a semiconductor substrate. A switching circuit is on a first portion of the insulating film. The switching circuit is configured to switch a path of a high-frequency signal. A wiring layer is provided on the insulating film. The wiring layering includes a signal wire and a ground wire. A conductive layer is between the wiring layer and the insulating film. The conductive layer, in some embodiments, includes a first conductive region between the high-frequency wiring and the insulating film and a second conductive region between the grounding wiring and the insulating film.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.

Abstract: A transient electronic device includes electronic elements (e.g., an SOI- or chip-based IC) and a trigger mechanism disposed on a frangible glass substrate. The trigger mechanism includes a switch that initiates a large trigger current through a self-limiting resistive element in response to a received trigger signal. The self-limiting resistive element includes a resistor portion that generates heat in response to the trigger current, thereby rapidly increasing the temperature of a localized (small) region of the frangible glass substrate, and a current limiting portion (e.g., a fuse) that self-limits (terminates) the trigger current after a predetermined amount of time, causing the localized region to rapidly cool down.

Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.

Abstract: A method may include providing a surface feature on a substrate, the surface feature comprising a feature shape a feature location, and a dimension along a first direction within a substrate plane; depositing a layer comprising a layer material on the surface feature; and directing ions in an ion exposure at an angle of incidence toward the substrate, the angle of incidence forming a non-zero angle with respect to a perpendicular to the substrate plane, wherein the ion exposure comprises the ions and reactive neutral species, the ion exposure reactively etching the layer material, wherein the ions impact a first portion of the surface feature and do not impact a second portion of the surface feature, and wherein an altered surface feature is generated, the altered surface feature differing from the surface feature in at least one of: the dimension along the first direction, the feature shape, or the feature location.

Abstract: Methods for forming layers on a substrate having a feature are provided herein. In some embodiments, a method for forming layers on a substrate having a features may include depositing a copper layer within the feature, wherein a thickness of the copper layer disposed on upper corners of an opening of the feature and on an upper portion of a sidewall proximate the upper corners of the feature is greater than the thickness of the copper layer disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature; and exposing the substrate to a plasma formed from a process gas comprising hydrogen (H2) gas to selectively etch the copper layer proximate the upper corners of the opening and the upper portion of the sidewall proximate the upper corners, without substantially etching the copper layer proximate the lower portion of the sidewall proximate the bottom of the feature.

Abstract: A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.

Abstract: A female structure embedding a first metal pillar and a male structure embedding a second metal pillar. The female structure and the male structure can be locked in with each other, the embedded first metal pillar electrically coupled to the second metal pillar through a metal block. The metal block is electrically coupled to a bottom surface of the first metal pillar, and the metal block wraps peripheral surface of a top end of the second metal pillar. A first embodiment shows the metal block is formed by electroless deposition after matching the female structure to the male structure. A second embodiment shows the metal block is a solder joint.

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.

Abstract: A tandem light-emitting element in which generation of crosstalk can be suppressed even when the element is applied to a high-definition display is provided. In the tandem light-emitting element, a layer in contact the anode side of an intermediate layer contains 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen).

Abstract: Dielectric treatments for carbon nanotube devices are provided. In one aspect, a method for forming a carbon nanotube-based device is provided. The method includes: providing at least one carbon nanotube disposed on a first dielectric; removing contaminants from surfaces of the first dielectric; and depositing a second dielectric onto the first dielectric and at least partially surrounding the at least one carbon nanotube. A carbon nanotube-based device is also provided.

Abstract: Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate.