Patents Examined by Calvin Choi
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Patent number: 9741966Abstract: Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The encapsulation methods may be performed as single or multiple chamber processes. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes.Type: GrantFiled: June 24, 2016Date of Patent: August 22, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Jrjyan Jerry Chen, Soo Young Choi
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Patent number: 9741568Abstract: The invention provides a sulfur doping method for graphene, which comprises the steps of: 1) providing graphene and placing the grapheme in a chemical vapor deposition reaction chamber; 2) employing an inert gas to perform ventilation and exhaust treatment in the reaction chamber; 3) introducing a sulfur source gas to perform sulfur doping on the graphene at 500-1050° C.; and 4) cooling the reaction chamber in a hydrogen and inert gas atmosphere. The present invention can perform sulfur doping on the graphene simply and efficiently, the economic cost is low, and large-scale production can be realized. Large area sulfur doping on graphene can be realized, and doping of graphene on an insulating substrate or metal substrate can be carried out directly.Type: GrantFiled: May 20, 2014Date of Patent: August 22, 2017Assignee: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCESInventors: Tie Li, Chen Liang, Yuelin Wang
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Patent number: 9735264Abstract: A semiconductor device includes a semiconductor body, at least one wiring layer disposed on the semiconductor body and a field effect transistor integrated in the semiconductor body. The field effect transistor has a plurality of gate electrodes residing in corresponding gate trenches formed in the semiconductor body. A first circuit is integrated in the semiconductor body adjacent to the field effect transistor, and a second circuit is integrated in the semiconductor body remote from the first circuit. A first additional trench is formed in the semiconductor body and includes at least one connecting line which electrically connects the first circuit and the second circuit. The semiconductor device also includes at least one conductive pad formed in the at least one wiring layer. The at least one conductive pad is arranged to at least partially cover the first additional trench to form a shielding of the at least one connecting line.Type: GrantFiled: August 31, 2015Date of Patent: August 15, 2017Assignee: Infineon Technologies AGInventors: Norbert Krischke, Bernhard Auer, Robert Illing
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Patent number: 9735066Abstract: A method and apparatus for use in surface delayering for fault isolation and defect localization of a sample work piece is provided. More particularly, a method and apparatus for mechanically peeling of one or more layers from the sample in a rapid, controlled, and accurate manner is provided. A programmable actuator includes a delayering probe tip with a cutting edge that is shaped to quickly and accurately peel away a layer of material from a sample. The cutting face of the delayering probe tip is configured so that each peeling step peels away an area of material having a linear dimension substantially equal to the linear dimension of the delayering probe tip cutting face. The surface delayering may take place inside a vacuum chamber so that the target area of the sample can be observed in-situ with FIB/SEM imaging.Type: GrantFiled: January 30, 2014Date of Patent: August 15, 2017Assignee: FEI CompanyInventors: Alexander Buxbaum, Michael Schmidt
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Patent number: 9735383Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.Type: GrantFiled: September 12, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
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Patent number: 9735088Abstract: A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side opposite the first side. The second side of the IC die is coupled to the carrier. The system includes a die attach layer between the carrier and the second side of the IC die. The die attach layer defines one or more openings that enable a fluid to flow from the carrier to the second side of the IC die.Type: GrantFiled: December 8, 2015Date of Patent: August 15, 2017Assignee: The Boeing CompanyInventors: Kyle A. Woolrich, Jonathan M. Allison, Thomas Rust, III, Robert E. Silhavy
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Patent number: 9721867Abstract: Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height.Type: GrantFiled: March 18, 2015Date of Patent: August 1, 2017Assignees: National Technology & Engineering Solutions of Sandia, LLC, Qorvo US, Inc.Inventors: Cody M. Washburn, Timothy N. Lambert, David R. Wheeler, Christopher T. Rodenbeck, Tarak A. Railkar
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Patent number: 9722083Abstract: An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium.Type: GrantFiled: October 17, 2013Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ziwei Fang
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Patent number: 9716027Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.Type: GrantFiled: January 27, 2016Date of Patent: July 25, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
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Patent number: 9711556Abstract: An image sensor structure includes a region of semiconductor material having a first major surface and a second major surface. A pixel structure is within the region of semiconductor material and includes a plurality of doped regions and a plurality of conductive structures. A metal-filled trench structure extends from the first major surface to the second major surface. A first contact structure is electrically connected to a first surface of the conductive trench structure, and a second contact structure electrically connected to a second surface of the conductive trench structure. In one embodiment, the second major surface is configured to receive incident light.Type: GrantFiled: December 12, 2016Date of Patent: July 18, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Rick Jerome, David T. Price, Sungkwon C. Hong, Gordon M. Grivna
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Patent number: 9711398Abstract: Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer.Type: GrantFiled: December 7, 2015Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ya-Lien Lee
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Patent number: 9711452Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.Type: GrantFiled: December 5, 2014Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson
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Patent number: 9704798Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.Type: GrantFiled: December 20, 2013Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Sridhar Govindaraju, Anindya Dasgupta, Rohit Grover
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Patent number: 9698069Abstract: Provided is a glass composition for protecting a semiconductor junction which contains at least SiO2, B2O3, Al2O3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50° C. to 550° C. falls within a range of 3.33×10?6 to 4.13×10?6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where “a glass material containing lead silicate as a main component” is used.Type: GrantFiled: March 7, 2016Date of Patent: July 4, 2017Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Koya Muyari, Koji Ito, Atsushi Ogasawara, Kazuhiko Ito
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Patent number: 9698305Abstract: A high voltage LED flip chip includes two or more regions; a Mesa-platform, the Mesa-platform in each region has a first groove; a first electrode located on the Mesa-platform, an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer covering the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, the fourth groove exposes a surface of the first electrode; and an interconnection electrode, the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region. The LED formed has improved performance.Type: GrantFiled: May 25, 2016Date of Patent: July 4, 2017Assignee: Enraytek Optoelectronics Co., Ltd.Inventors: Huiwen Xu, Yu Zhang, Qiming Li
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Patent number: 9698197Abstract: A high-voltage flip LED chip and a manufacturing method thereof. In the high-voltage flip LED chip, a P-N electrode connecting metal block is filled into an isolation trench between two adjacent chip units and is respectively filled into a first electrode hole of one chip unit and a second electrode hole of the other chip unit to serially connect the two adjacent chips.Type: GrantFiled: June 8, 2016Date of Patent: July 4, 2017Assignee: ENRAYTEK OPTOELECTRONICS CO., LTD.Inventors: Huiwen Xu, Yu Zhang, Qiming Li
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Patent number: 9698301Abstract: A wafer processing method for dividing a wafer (including a substrate and a functional layer formed on the front side of the substrate) along a plurality of division lines. The functional layer is partitioned by the division lines to define a plurality of regions. The method includes the following steps: attaching a protective member to the front side of the wafer; cutting the back side of the substrate of the wafer in an area corresponding to each division line with a cutting blade, thereby forming a division groove having a depth not reaching the functional layer so that a part of the substrate is left in this area; applying a laser beam to the wafer from the back side of the substrate along the bottom of each division groove extending along each division line to thereby cut the part of the substrate and the functional layer along each division line.Type: GrantFiled: October 27, 2016Date of Patent: July 4, 2017Assignee: Disco CorporationInventors: Yuki Ogawa, Yohei Yamashita, Tsubasa Obata
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Patent number: 9685407Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.Type: GrantFiled: September 9, 2016Date of Patent: June 20, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson
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Patent number: 9673299Abstract: The present invention relates to the field of manufacturing technologies of semiconductor power devices, and more particularly to a method for manufacturing a split-gate power device. In the method for manufacturing a split-gate power device according to the present invention, lateral etching is added to form lateral recesses of a control gate groove below a first insulating film in a process of forming the control gate groove by etching, and therefore, after a first conductive film is deposited, the first conductive film can be directly etched by using the first insulating film as a mask to form control gates. The technical process of the present invention is simplified, reliable and easy to control, and can greatly improve the yield of the split-gate power device. The present invention is particularly suitable for the manufacture of 25V-200V semiconductor power devices.Type: GrantFiled: March 15, 2016Date of Patent: June 6, 2017Assignee: SU ZHOU ORIENTAL SEMICONDUCTOR CO., LTD.Inventors: Zhendong Mao, Lei Liu, Wei Liu, Minzhi Lin
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Patent number: 9673044Abstract: Group III nitride substrate having a first side of nonpolar or semipolar plane and a second side has more than one stripe of metal buried, wherein the stripes are perpendicular to group III nitride's c-axis. More than 90% of stacking faults exist over metal stripes. Second side may expose a nonpolar or semipolar plane. Also disclosed is a group III nitride substrate having a first side of nonpolar or semipolar plane and a second side with exposed nonpolar or semipolar plane. The substrate contains bundles of stacking faults with spacing larger than 1 mm. The invention also provides methods of fabricating the group III nitride substrates above.Type: GrantFiled: December 4, 2015Date of Patent: June 6, 2017Assignee: SixPoint Materials, Inc.Inventor: Tadao Hashimoto