Abstract: A mask frame assembly includes a mask having pattern openings and a frame including a first support portion configured to support an end of the mask and having a clamping slot and a support slot adjacent to the clamping slot; and a second support portion connected to the first support portion.

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract: The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the on-wafer de-embedding dummy; obtaining the intrinsic Y-parameter admittance matrix of said N on-wafer de-embedding dummies by calculation or simulation by using said models; and solving the equation set which the corresponding measurement and calculation or simulation data of said on-wafer de-embedding dummies satisfy for the elements of the related admittance matrices of the parasitic four-port network to be stripped in de-embedding and model parameters of models on which said calculation or simulation is based.

Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface. Methods include soaking a substrate surface comprising hydroxyl-terminations with a silylamine to form silyl ether-terminations and depositing a film onto a surface other than the silyl ether-terminated surface.

Abstract: A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial spaces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. A healing layer is formed on the spacer layer to fill the cleavages of the first interstitial spaces. The healing layer is formed to provide second interstitial spaces respectively located in the first interstitial spaces as well as to include a polymer material.

Abstract: A package structure and a method of fabricating the same are provided. The method includes forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, encapsulating the first wiring layer and the first conductors with a first insulating layer, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, encapsulating the second wiring layer and the second conductors with a second insulating layer, and forming at least one opening in the second insulating layer. The at least one opening extends to a second surface of the first insulating layer, such that at least one electronic component can be disposed in the at least one opening. With forming two insulating layers first followed by forming the at least one opening, there is no need to stack or laminate the substrate that already has an opening, and the electronic component is free of displacement due to any compression.

Abstract: A thin film transistor array substrate includes a thin film transistor including a first gate electrode, an active layer, a source electrode, and a drain electrode. A first conductive layer pattern is on a same layer as the source electrode and the drain electrode and formed of a same material as the source electrode and the drain electrode. An insulating layer is on the first conductive layer pattern and has an opening exposing a patterning cross-section of the first conductive layer pattern. A pixel electrode is on the insulating layer and is coupled to the source electrode or the drain electrode through a contact hole passing through the insulating layer. A diffusion prevention layer covers the patterning cross-section of the first conductive layer pattern and inclined side surfaces of the insulating layer exposed through the opening.

Abstract: The present invention relates to a liquid-phase method for doping a semiconductor substrate, characterized in that a first composition containing at least one first dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the first composition; a second composition containing at least one second dopant is applied to one or more regions of the surface of the semiconductor substrate, in order to create one or more region(s) of the surface of the semiconductor substrate coated with the second composition, where the one or more region(s) coated with the first composition and the one or more region(s) coated with the second composition are different and do not overlap significantly and where the first dopant is an n-type dopant and the second dopant is a p-type dopant or vice versa; the regions of the surface of the semiconductor substrate coated with the first composition and with the

Abstract: This disclosure relates to methods for manufacturing devices capable of functioning as thermoelectric generators and related objects by the process of additive manufacturing or by 3-D printing or by casting. This disclosure also particularly relates to the uses of the thermoelectric generators and related objects produced by these methods.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu—Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.

Abstract: Provided are substrate processing systems and methods of managing the same. The method may include displaying a notification for a preventive maintenance operation on a chamber, performing a maintenance operation on the chamber, performing a first optical test, and evaluating the preventive maintenance operation. The first optical test may include generating a reference plasma reaction, measuring a variation of intensity by wavelength for plasma light emitted from the reference plasma reaction, and calculating an electron density and an electron temperature from a ratio in intensity of the plasma light.

Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract: A method of forming a semiconductor device includes forming a dielectric layer over a substrate, and curing the dielectric layer with a first curing process. The first curing process includes providing a first UV light source, filtering the first UV light source with a first filter, the first filter permitting a first electromagnetic radiation within a first pre-determined spectrum to pass through and blocking electromagnetic radiation outside the first pre-determined spectrum, and curing the dielectric layer with the first electromagnetic radiation of the first UV light source.

Abstract: Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

Abstract: Embodiments of methods and apparatus for correcting substrate deformity are provided herein. In some embodiments, a substrate flattening system includes: a first process chamber having a first substrate support and a first showerhead, wherein the first substrate support does not include a chucking mechanism; a first heater disposed in the first substrate support to heat a substrate placed on a first support surface of the first substrate support; a second heater configured to heat a process gas flowing through the first showerhead into a first processing volume of the first process chamber; and a second process chamber having a second substrate support, wherein the second substrate support is not heated, and wherein the first process chamber and the cooling chamber are both non-vacuum chambers.

Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.