Abstract: The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: The invention relates to a process for the production of electrolyte capacitors having a low equivalent series resistance and low residual current for high nominal voltages, electrolyte capacitors produced by this process and the use of such electrolyte capacitors.

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract: A tandem light-emitting element in which generation of crosstalk can be suppressed even when the element is applied to a high-definition display is provided. In the tandem light-emitting element, a layer in contact the anode side of an intermediate layer contains 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen).

Abstract: A thin film having a low dielectric constant and a high resistance to HF at a low temperature range is formed with high productivity. A film containing a predetermined element, oxygen and at least one of carbon and nitrogen is formed on a substrate by performing, a predetermined number of times, a cycle comprising: (a) supplying a source gas containing the predetermined element to the substrate; and (b) supplying a reaction gas containing nitrogen, carbon and oxygen to the substrate.

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract: An organic light emitting display device including a thin film transistor including an active layer, a gate electrode, a source electrode, a drain electrode, a source electrode top layer on the source electrode and a drain electrode top layer on the drain electrode, a first insulating layer between the active layer and the gate electrode, and a second insulating layer between the gate electrode and the source and drain electrodes; a pad electrode including a first pad layer at the same level as the source electrode and a second pad layer on the first pad layer and at the same level as the source and drain electrode top layers; a third insulating layer covering end portions of the source, drain, and pad electrodes and including an organic insulating layer; and a pixel electrode in an opening formed in the third insulating layer and including a semi-transmissive metal layer.

Abstract: A method for fabricating a LDMOS device in a semiconductor substrate of a first doping type, including: implanting a series of dopants into the semiconductor substrate using a first mask, and forming a first region of a second doping type adjacent to the surface of the semiconductor substrate, a second region of the first doping type located beneath the first region, and a third region of the second doping type located beneath the second region; implanting dopants into the semiconductor substrate using a second mask, and forming a fourth region of the second doping type adjacent to the first, second and third regions, wherein the fourth region extends from the surface of the semiconductor substrate to approximately the same depth as the third region; and implanting dopants into the first region using a third mask, and form a first well of the first doping type.

Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.

Abstract: An organic material deposition device configured to sense a deposition amount of an organic material deposited in a vacuum chamber by detecting a back propagation characteristic variation of a passive radio frequency identification (RFID) sensor. The organic material deposition device includes: a chamber configured to perform an organic material deposition process therein; a deposition source mounted in the chamber to vaporize an organic material; a deposition mask mounted to face the deposition source and configured to bond a substrate at an opposite side to the deposition source; an antenna mounted in the chamber to receive back propagation from a radio frequency identification (RFID) sensor; and a radio frequency (RF) reader connected to the antenna to measure an organic material deposition amount from a variation of the back propagation.

Abstract: An optoelectronic component is specified. According to at least one embodiment of the invention, the optoelectronic component comprises a housing (20) and a radiation-emitting or radiation-receiving semiconductor chip (10) arranged in the housing (20). Furthermore, the component comprises an optical element (50), which contains a polymer material comprising a silicone. The silicone contains at least 40% by weight of cyclic siloxanes, and at least 40% of the silicon atoms of the cyclic siloxanes are crosslinked with a further silicon atom of the silicon via alkylene and/or alkylarylene groups.

Abstract: The invention relates to a method for producing an electrode layer of an electrical device, wherein the method includes the following steps: providing a quantity of nanoparticles from an electrically conductive material, the surfaces of each of which have a layer of a hygroscopic stabilizer material, preparing a substrate and producing an electrode layer on a substrate surface, wherein the nanoparticles in this context are deposited on the substrate surface and are tempered in a solvent atmosphere of a polar solvent.

Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure.

Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.

Abstract: A thin film that has a predetermined composition and containing predetermined elements is formed on a substrate by performing a cycle of steps a predetermined number of times, said cycle comprising: a step wherein a first layer containing the predetermined elements, nitrogen and carbon is formed on the substrate by alternately performing, a predetermined number of times, a process of supplying a first source gas containing a predetermined element and a halogen group to the substrate and a process of supplying a second source gas containing a predetermined element and an amino group to the substrate; a step wherein a second layer is formed by modifying the first layer by supplying an amine-based source gas to the substrate; and a step wherein a third layer is formed by modifying the second layer by supplying a reaction gas that is different from the source gases to the substrate.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.