Patents Examined by Calvin Choi
  • Semiconductor devices with sidewall spacers of equal thickness
    Patent number: 9576961
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Balasubramanian Pranatharthiharan, Soon-Cheon Seo
  • Power semiconductor device
    Patent number: 9577080
    Abstract: A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Holger Huesken, Frank Dieter Pfirsch, Hans-Joachim Schulze
  • Power semiconductor package with integrated heat spreader and partially etched conductive carrier
    Patent number: 9570379
    Abstract: In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Method for forming a semiconductor image sensor device
    Patent number: 9570494
    Abstract: In one embodiment, a method for forming a backside illuminated image sensor includes providing a region of semiconductor material having a first major surface and a second major surface configured to receive incident light. A pixel structure is formed within the region of semiconductor material adjacent the first major surface. Thereafter, a trench structure comprising a metal material is formed extending through the region of semiconductor material. A first surface of the trench structure is adjacent the first major surface of the region of semiconductor material and a second surface adjoining the second major surface of the region of semiconductor material. A first contact structure is electrically connected to one surface of the conductive trench structure and a second contact structure is electrically connected to an opposing second surface.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: February 14, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rick Jerome, David T. Price, Sungkwon C. Hong, Gordon M. Grivna
  • Localized elastic strain relaxed buffer
    Patent number: 9570298
    Abstract: A strain relaxed buffer layer is fabricated by melting an underlying layer beneath a strained semiconductor layer, which allows the strained semiconductor layer to elastically relax. Upon recrystallization of the underlying layer, crystalline defects are trapped in the underlying layer. Semiconductor layers having different melting points, such as silicon germanium layers having different atomic percentages of germanium, are formed on a semiconductor substrate. An annealing process causes melting of only the silicon germanium layer that has the higher germanium content and therefore the lower melting point. The silicon germanium layer having the lower germanium content is elastically relaxed upon melting of the adjoining silicon germanium layer and can be used as a substrate for growing strained semiconductor layers such as channel layers of field-effect transistors.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Thin film transistor array panel
    Patent number: 9559127
    Abstract: A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (?) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Daisuke Inoue, Mi Suk Kim, Si Heun Kim, Tae Ho Kim, So Youn Park, Keun Chan Oh, Chang-Hun Lee
  • Field effect transistors and methods of forming same
    Patent number: 9559168
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: January 31, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Der-Chuan Lai, Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
  • Integrated circuit and method of fabricating the same
    Patent number: 9553140
    Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung, Ho-Chun Liou
  • Backside redistribution layer (RDL) structure
    Patent number: 9553059
    Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Jing-Cheng Lin
  • Electronic device, image display apparatus, and substrate for configuring image display apparatus
    Patent number: 9548465
    Abstract: An electronic device includes a first electrode and a second electrode which are separately formed on a base; a functional layer which includes an organic semiconductor material layer, and is formed on the base between the first electrode and the second electrode; a functional layer extension portion which includes the organic semiconductor material layer, and extends from the functional layer; a protective film which is formed at least on the functional layer; and an insulating layer which covers an entire surface, in which the protective film is patterned to include at least two sides which intersect with each other at an acute angle, and a vertex portion of the protective film in which the two sides intersect with each other, is chamfered.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: January 17, 2017
    Assignee: Sony Corporation
    Inventor: Ryuto Akiyama
  • Vapor deposition apparatus, deposition method using the same, and method of manufacturing organic light-emitting display apparatus
    Patent number: 9543518
    Abstract: A vapor deposition apparatus for forming a deposition layer on a substrate includes a supply unit that is supplied with a first raw gas to form the deposition layer and an auxiliary gas, wherein the auxiliary gas does not constitute a raw material to form the deposition layer, a reaction space that is connected to the supply unit to be supplied with the first raw gas and the auxiliary gas, a plasma generator in the reaction space to convert at least a portion of the first raw gas into a radical form, and a first injection portion that is connected to the reaction space and that supplies at least a radical material of the first raw gas toward the substrate.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: January 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Hyun Kim, Myung-Soo Huh
  • Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and recording medium
    Patent number: 9543220
    Abstract: According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: January 10, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Takeo Sato
  • Image sensor integrated circuit package with reduced thickness
    Patent number: 9530818
    Abstract: An image sensor die may include a pixel array formed in an image sensor substrate. The image sensor die may be mounted to a thin metal interconnect layer that has been deposited on a sacrificial carrier substrate. The thin metal interconnect layer may include one or more metal layers that are patterned to form metal traces that serve as contact pads, signal lines, and other interconnects in the interconnect layer. The image sensor die may be wire bonded, flip-chip mounted, or otherwise mechanically and electrically coupled to the metal interconnect layer. The sacrificial carrier substrate may be etched or otherwise removed to expose the metal interconnects on the metal interconnect layer. An array of solder balls may be formed on the exposed metal interconnects to form a ball grid array package, or the exposed contact pads may be plated to form a leadless chip carrier package.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 27, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jonathan Michael Stern
  • Apparatus and method for self-aligning chip placement and leveling
    Patent number: 9530673
    Abstract: An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Kuo-Chung Yee
  • Semiconductor package, semiconductor device and method of forming the same
    Patent number: 9530762
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng
  • Semiconductor process for forming gates with different pitches and different dimensions
    Patent number: 9525041
    Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Line layout and method of spacer self-aligned quadruple patterning for the same
    Patent number: 9524878
    Abstract: A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 20, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chi-Sheng Peng
  • Electronic device
    Patent number: 9524953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Semiconductor device comprising an e-fuse and a FET
    Patent number: 9524962
    Abstract: A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andrei Sidelnicov, Andreas Kurz, Alexandru Romanescu
  • Atomic layer etch process using an electron beam
    Patent number: 9520294
    Abstract: Atomic layer etching using alternating passivation and etching processes is performed with an electron beam plasma source, in which the ion energy is set to a low level below the etch threshold of the material to be etched during passivation and to a higher level above the etch threshold during etching but below the etch threshold of the unpassivated material.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 13, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ankur Agarwal, Rajinder Dhindsa, Shahid Rauf