Abstract: A method of manufacturing a switching element is provided. The method includes forming a pillar-shaped structure having a first electrode, an insulation layer and a second electrode which are stacked on a substrate. A tilted doping process is performed to inject dopants into at least a portion of the insulation layer. The tilted doping process forms a threshold switching operation region in the insulation layer.

Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.

Abstract: A nitride semiconductor light emitting device includes a substrate as a base and an n-type semiconductor layer grown on a surface side of the substrate. Antimony (Sb) is added to the n-type semiconductor layer so that a molar fraction is not less than 0.1% and is less than 1%. A concentration of an n-type impurity in the n-type semiconductor layer is lower than an electron concentration.

Abstract: Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

Abstract: A semiconductor light emitting apparatus comprised of a semiconductor light emitting device (100) having a layered semiconductor layer (110) configured by layering at least two or more semiconductor layers (103), (105) and a light emitting layer (104) to emit first light, and a wavelength conversion member that covers at least apart of the semiconductor light emitting device (100), absorbs at least a part of the first light and that emits second light with a wavelength different from that of the first light, characterized in that the semiconductor light emitting device (100) is provided with a fine structure layer, as a component, including dots comprised of a plurality of convex portions or concave portions extending in the out-of-plane direction on one of main surfaces forming the semiconductor light emitting device (100), the fine structure layer forms a two-dimensional photonic crystal (102) controlled by at least one of a pitch among the dots, a dot diameter and a dot height, and that the two-dimensional

Abstract: In at least one embodiment, the semiconductor component includes at least one optoelectronic semiconductor chip having a radiation exit side. The surface-mountable semiconductor component comprises a shaped body that covers side surfaces of the semiconductor chip directly and in a positively locking manner. The shaped body and the semiconductor chip do not overlap, as seen in a plan view of the radiation exit side.

Abstract: The present disclosure provides a TFT array substrate and manufacturing method thereof, forming a class structure of graphene-like two-dimensional layered semiconductor material on a base substrate and transferring the class structure of graphene-like two-dimensional layered semiconductor material on the designated position of the soft substrate to be a semiconductor active layer of the array substrate, therefore the semiconductor active layer of the TFT array substrate of the present disclosure uses a class structure of graphene-like two-dimensional layered semiconductor material to makes the array substrate having the advantage of higher electron mobility and mechanical property, excellent flexural resistance and reducing thickness of the substrate greatly.

Abstract: The present disclosure relates to a packaging process using a low pressure encapsulant. According to an exemplary process, an assembly including a substrate, a surface mounted device (SMD) mounted on the substrate, and a space between the SMD and the substrate is provided. The SMD has a sealed cavity biased towards the substrate. A sheet mold compound is laid over the SMD and the assembly is heated such that the sheet mold compound transitions to a liquid phase to form a molten mold compound. Next, the assembly is subjected to a vacuum that creates a negative atmosphere allowing the molten mold compound to flow towards the top surface of the substrate and about the SMD. The molten mold compound is then pressed towards the substrate at a low pressure (<=2 Mpa) such that the space between the SMD and the substrate is substantially filled and the SMD is substantially encapsulated.

Abstract: In accordance with certain embodiments, electronic components such as light-emitting elements are bonded to connection points on a substrate via pressure applied via a membrane and curing of a pressure-activated adhesive.

Abstract: A MEMS device. The device includes a membrane, and a reinforced backplate having a plurality of openings. The reinforced backplate include a first layer, and a second layer coupled to the first layer.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.

Abstract: An organic light-emitting display apparatus includes a substrate, an optical layer formed over the substrate and a light emitting pixel formed over the optical layer. The optical layer includes a first refractive index layer portion having a first refractive index, a second refractive index layer portion having a second refractive index greater than the first refractive index. The second portion is disposed next to the first portion and contacts the first portion. The light emitting pixel includes a pixel electrode overlapping the first portion and comprising a first reflective layer, a pixel-defining film overlapping the second portion, an intermediate layer formed over the pixel electrode and comprising an organic light emission layer, and an opposite electrode formed over and overlapping the intermediate layer and the pixel-defining film and comprising a second reflective layer.

Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.

Abstract: A nanostructure layer includes a number of nanostructures, wherein the number of nanostructures are aligned along a number of straight lines, a size of each of the number of nanostructures ranges from about 20 nanometers to about 100 nanometers, a distance between adjacent two nanostructures ranges from about 10 nanometers to about 300 nanometers, and each of the number of nanostructures includes a core and a shell coated on the core. A light emitting diode with the nanostructure layer is also provided.

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.

Abstract: An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.

Abstract: A method of manufacturing a light-emitting device includes forming a separation layer on an upper surface of a supporting substrate; forming a plurality of external electrode layers on the separation layer; mounting a plurality of light-emitting elements on the external electrode layers; forming a plurality of resin layers between the supporting substrate and each of the light-emitting elements after mounting the light-emitting elements, the resin layers being formed such that the resin layers are separated from one another, and each resin layer underlies at least one light-emitting element; and applying laser light to the separation layer from a lower surface side of the supporting substrate, and separating the supporting substrate and the light-emitting elements from each other.