Abstract: A 3D semiconductor device, the device including: a first die comprising first transistors and a first interconnect; and a second die comprising second transistors and a second interconnect, wherein said first die is overlaid by said second die, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is pretested, wherein said second die is bonded to said first die, wherein said bonded comprises metal to metal bonding, wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

Abstract: Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.

Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage.

Abstract: A method for producing a microelectromechanical component as well as a wafer system includes steps of: providing a first wafer having a plurality of microelectromechanical base elements; forming a respective container structure on the microelectromechanical base elements at the wafer level; and disposing an oil or a gel within the container structures.

Abstract: A downhole closed loop method for controlling a drilling toolface includes measuring first and second attitudes of the subterranean borehole at corresponding first and second upper and lower survey stations. The first and second attitudes are processed downhole while drilling to compute an angle change of the subterranean borehole between the upper and lower survey stations. The computed angle change is compared with a predetermined threshold. This process may be continuously repeated while the angle change is less than the threshold. The first and second attitudes are further processed downhole to compute a toolface angle when the angle change of the subterranean borehole is greater than or equal to the threshold. The toolface angle may then be further processed to control a direction of drilling of the subterranean borehole.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

Abstract: A method for transferring semiconductor bodies and a semiconductor chip are disclosed.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.

Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Abstract: A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

Abstract: A display including a bending region is provided. The display includes a pixel layer including a plurality of pixel and a substrate disposed under the pixel layer and including a first area on which the pixel layer is disposed and a second area extending out of the pixel layer from the first area, at least a partial area of the second area being bendable, wherein the substrate includes: a wiring layer including at least one first wiring electrically connected with at least one pixel of the plurality of pixels and connected from the first area to the second area, and at least one second wiring disposed in the at least partial area and electrically connected with the at least one first wiring in the second area. Further, other embodiments may be possible.

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

Abstract: In accordance with certain embodiments, a light-emitting element composed of one or more discrete units configured for light emission is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the light-emitting element or non-coplanarity of the semiconductor die contacts.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A display device includes a substrate, a pad electrode, a pixel electrode, an opposite electrode, an encapsulation member, a planarization layer, and a conductive layer. The substrate includes a display region and a peripheral region. The pad electrode is disposed on the substrate in the peripheral region. The pixel electrode and the opposite electrode are disposed on the substrate in the display region. The encapsulation member is disposed on the opposite electrode. The planarization layer is disposed on the encapsulation member in the display region and the peripheral region. The conductive layer is disposed on the planarization layer. The planarization layer includes a contact hole exposing at least a portion of the pad electrode. The conductive layer contacts the portion of the pad electrode exposed through the contact hole.

Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

Abstract: Some embodiments include an integrated assembly which has bitline structures that extend along a first direction. The bitline structures include conductive bitlines, and include insulative shells which extend over the conductive bitlines and along sidewalls of the conductive bitlines. The insulative shells include a first silicon nitride composition. The bitline structures are spaced from one another by intervening regions. Semiconductor structures and insulative spacers are within the intervening regions. The semiconductor structures and insulative spacers alternate with one another along the first direction. The insulative spacers include a second silicon nitride composition which is characterized as having a faster etch rate than the first silicon nitride composition by a mixture which contains sulfuric acid and hydrogen peroxide. Some embodiments include methods of forming integrated assemblies.

Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes a first layer and a second layer. The second layer includes a different conductive material as the first layer. A portion of the second layer is disposed above and directly contacts a portion of the first layer.