Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.

Abstract: A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

Abstract: A semiconductor device includes a semiconductor body, a first electrode on a back surface of the semiconductor body, second and third electrodes provided on a front surface of the semiconductor body, a first film linking the second electrode and the third electrode, and a second film between the semiconductor body and the first film. The first film has a higher resistivity than the first semiconductor body, and the second film is insulative. The second film includes a first-film-thickness portion and a second-film-thickness portion. The first-film-thickness portion has a first film thickness along a first direction directed from the first electrode toward the second electrode. The second-film-thickness portion has a second film thickness along the first direction thicker than the first film thickness. The first-film-thickness portion and the second-film-thickness portion surround the second electrode.

Abstract: A method includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions.

Abstract: An organic light-emitting display device includes a pixel electrode, an emission layer on the pixel electrode, an opposing electrode covering the emission layer, a plurality of upper layers on the opposing electrode, light-shielding elements on the upper layers, and a color filter layer on the upper layers. The light-shielding elements include first light-shielding layers and second light-shielding layers. The first light-shielding layers include first materials, and the second light-shielding layers include second materials different from the first materials. The second light-shielding layers overlay the first light-shielding layers.

Abstract: A packaged semiconductor device includes at least one semiconductor die having circuitry with circuit nodes coupled to bond pads that have bonding features thereon. A plurality of leads or lead terminals include at least metal bars, wherein the plurality of leads or lead terminals are exclusive of any saw marks. The semiconductor die is flipchip attached with a bonded connection between respective bonding features and respective leads or lead terminals.

Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.

Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

Abstract: A semiconductor device includes a substrate including a resistor region, a plurality of lower patterns in the resistor region, and a resistor line pattern on the plurality of lower patterns and the substrate of the resistor region. The plurality of lower patterns extend in a first direction parallel to a surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction and parallel to the surface of the substrate. The resistor line pattern extends in the second direction. The resistor line pattern on the lower patterns has an upper surface and a lower surface protruding in a third direction perpendicular to the surface of the substrate.

Abstract: An electroluminescent display device and a fabricating method thereof are provided. The device has a TFT layer, a first functional layer, an electroluminescent layer, a second functional layer, and a functional bar disposed sequentially. The device uses Seebeck effect of constituent material of p-type Bi2Te3 of the functional bar to absorb heat of the TFT layer for converting the heat into electric energy, thereby effectively reducing heat of the TFT layer, reducing aging of circuit and organic material, and improving life of the electroluminescent display device. A work function of p-type Bi2Te3 material of the functional bar is 5.3 eV. An electroluminescent material has a HOMO energy level ranging from 5 to 6 eV. Under a driving of a thermoelectromotive force, majority carriers (holes) in the constituent material of p-type Bi2Te3, are injected into the electroluminescent layer to improve a carrier concentration therein, thereby improving emission luminance of the electroluminescent display device.

Abstract: An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.

Abstract: An electrode having an embedded charge contains a substrate, a first electronic charge trap defined at the interface of a first insulating layer and a second insulating layer; and a first conductive layer disposed on the first electronic charge trap; wherein the first conductive layer contains a conductive material configured to permit an external electric field to penetrate the electrode from the first electronic charge trap; and wherein the first insulating layer is not the same as the second insulating layer.

Abstract: An organic light-emitting diode (OLED) device includes an active layer of a transistor disposed on the buffer insulating film. A gate insulating film is disposed on the buffer insulating film over the conducting layer and disposed on the active layer. A gate electrode is disposed on the gate insulating film over a channel region of the active layer. A first connecting pattern is disposed on the gate insulating film over the conducting line and the active layer. The first connecting pattern is connected to the conducting layer via a first connecting contact hole through the gate insulating film and the buffer insulating film. The first connecting pattern is also connected to the active layer via a second connecting contact hole through the gate insulating film. The first connecting pattern has a same material as the gate electrode.

Abstract: Provided are an adhesive composition and an organic electronic device (OED) including the same, and more particularly, an adhesive composition, which may form a structure effectively blocking moisture or oxygen flowing into an OED from the outside, thereby ensuring the lifespan of the OED, realize a top-emission OED, and exhibit excellent adhesive durability and reliability, and excellent reliability at high temperature and high humidity, and an OED including the same.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.

Abstract: The present application discloses a display panel and a display device apparatus. The display panel includes a substrate, the substrate includes a plurality of pixel regions; an active switch, a plurality of active switches disposed on the substrate, wherein the pixel regions are disposed on the active switches, the active switches are corresponding to each of the pixel regions, respectively, and each of the active switch includes: an insulating layer, the insulating layer includes at least two thin film layers, the thin film layers are formed by chemical vapor deposition process with a predetermined thickness.

Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.