Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

Abstract: A sub-pixel structure including: a light emitting device including a first electrode layer and a second electrode layer arranged opposite to each other, the first electrode layer and the second electrode layer together defining an optical microcavity. A first refractive layer is provided at a light exit surface of the light emitting device, the first refractive layer operable to reflect a portion of light emitted by the light emitting device back into the optical microcavity for interference. A second refractive layer is provided at a side of the first refractive layer facing away from the light exit surface, the second refractive layer operable to reflect a portion of the light emitted by the light emitting device and transmitted through the first refractive layer back into the optical microcavity for interference.

Abstract: A display device including a pixel circuit, an insulation layer covering the pixel circuit, an etching prevention layer disposed on the insulation layer, a first guide layer, a second guide layer, a first electrode, a second electrode, and a light emitting element. The first guide layer and the second guide layer may be disposed on the etching prevention layer and spaced apart from each other. The first electrode may be disposed on the first guide layer and electrically connected to the pixel circuit. The second electrode may be disposed on the first guide layer and insulated from the first electrode. The light emitting element may be in contact with the top surface of the etching prevention layer, disposed between the first guide layer and the second guide layer on a plane, and electrically connected to the first electrode and the second electrode.

Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

Abstract: A method for fabricating an (Al,Ga,In,B)N or III-nitride semiconductor device, including performing a growth of III-nitride or (Al,Ga,In,B)N material including a p-n junction with an active region and using metal-organic chemical vapor deposition (MOCVD) or chemical vapor deposition; and performing a subsequent regrowth of n-type (Al,Ga,In,B)N or III-nitride material using MOCVD or chemical vapor deposition while utilizing a pulsed delta n-type doping scheme to realize an abrupt, smoother surface of the n-type material and a higher carrier concentration in the n-type material. In another example, the method comprises forming a mesa having a top surface; and activating magnesium in the p-type GaN of the (Al,Ga,In,B)N material through openings in the top surface that expose the p-type GaN's surface. The openings are formed before or after the subsequent regrowth of the tunnel junction.

Abstract: Disclosed is an image sensor having a plurality of groups of pixels, each group of pixels including: first to third image detection color filter sets and a phase difference detection color filter set, which are arranged in a matrix with rows and columns. The phase difference detection color filter set comprises first to fourth phase difference detection color filter pairs arranged in a matrix with rows and columns. The first to fourth phase difference detection color filter pairs comprise first to fourth left phase difference detection color filters positioned on the left of each of the first to fourth phase difference detection color filter pairs and first to fourth right phase difference detection color filters positioned on the right of each of the first to fourth phase difference detection color filter pairs, respectively.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: An antifuse OTP memory bit cell comprises a gate electrode, a gate dielectric and source/drain diffusions formed in an active area of a semiconductor substrate. The source/drain diffusions are connected under the gate electrode by lateral diffusion but they don't have to be. If connected, a rectifying contact is created in a programmed bit cell. If unconnected, a rectifying contact or a non-rectifying contact is created in a programmed bit cell. Whether connected or unconnected, the device operates as an OTP memory bit cell without an access transistor.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.

Abstract: Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.

Abstract: A semiconductor integrated circuit includes: implanting impurity ions of a p-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of an n?-type to form first ion implantation regions; implanting the impurity ions of the p-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer to form second ion implantation regions; activating the impurity ions in the first ion implantation regions to form a well region, and activating the impurity ions in the second ion implantation regions to form a body region; forming a control element including first and second terminal regions of the n+-type in an upper portion of the well region; and forming an output-stage element including an output terminal region of the n+-type in an upper portion of the body region to be controlled by the control element.

Abstract: The present invention provides a light emitting layer structure and a display device, the light emitting layer structure includes a first charge injection layer disposed on the substrate and located in the pixel opening region; a metal reflective layer disposed on the first charge injection layer; the beneficial effects of the present invention is that in the light-emitting layer structure and display device of the present invention, the lengthwise direction of the metal reflective layer is longer than the lengthwise direction of the pixel opening region, can perform secondary irradiation to decompose the organic impurities remaining at the short arc-shape side and improve spreadability of the ink.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The method includes: providing a first substrate; forming first via holes into a first surface; forming a first metal layer on the first surface and in the first via holes; patterning the first metal layer to form first portions, including first sub-portions in the first via holes; forming second via holes into a second surface; forming a second metal layer on the second surface and in the second via holes; patterning the second metal layer to form second portions and pads, that the second portions and the pads are electrically connected, the second portions includes second sub-portions in the second via holes, and the first sub-portions and the second sub-portions are electrically connected; and bonding and electrically connecting electronic components with the plurality of pads.

Abstract: A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced.

Abstract: A light emitting transducer including a flexible sheet having a bottom side and a top side, the flexible sheet including a substrate that is stretchable and compressible, the substrate having a bottom substrate surface at the bottom side, and a top substrate surface facing towards the top side, the top substrate surface comprising a surface pattern of a plurality of raised and depressed micro-scale surface portions which extend in at least one direction; a light emitting diode layer above the substrate and conforming in shape to the top substrate surface, the light emitting diode layer corresponding with the surface pattern of the top substrate surface, wherein the light emitting diode layer has a bottom diode surface facing towards the bottom side, and a top diode surface facing towards the top side, a bottom electrode on the bottom diode surface, and a top electrode on the top diode surface.

Abstract: Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes on the respective bonding surfaces are in direct contact with each other. The electrode junction structure is for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer has a structure in which a protective film for prevention of diffusion of an electrically-conductive material constituting the electrode and the via is inside the electrically-conductive material.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a gate-cut isolation structure. An example method of fabricating semiconductor device generally includes forming a dielectric region between a first semiconductor region and a second semiconductor region. The method also includes forming a first gate region disposed above and spanning a width of the dielectric region between the first and second semiconductor regions, wherein the first gate region is also disposed above at least a portion of the first semiconductor region and above at least a portion of the second semiconductor region. The method further includes concurrently forming an SDB and a gate-cut isolation structure, wherein the SDB intersects the first and second semiconductor regions and wherein the gate-cut isolation structure electrically separates the first gate region into a first portion associated with the first semiconductor region and a second portion associated with the second semiconductor region.

Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor layer sequence having an active region configured to emit radiation, a dielectric layer, a solder layer including a first metal arranged on the dielectric layer and a seed layer arranged between the solder layer and the dielectric layer, wherein the seed layer includes the first metal and a second metal, wherein the second metal is less noble than the first metal, wherein an amount of the second metal in the seed layer is between 0.5 wt % and 10 wt %, and wherein the first metal is Au and the second metal is Zn.

Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.