Abstract: The present disclosure provides an organic light emitting diode display package structure and a method of manufacturing the same. The organic light emitting diode display package structure is provided with a gate insulating layer, a first barrier layer, a first organic buffer layer, a first hydrophobic layer, a second organic buffer layer, and a second barrier layer which are disposed sequentially. A double layer of the organic buffer layer has a thickness capable of wrapping the foreign matters in the area to lower the possibility that the water and oxygen pass through this area and enter OLED device to enhance the protection ability of the TFE on the OLED device.

Abstract: Examples described herein provide for methods for semiconductor processing for forming source/drain regions of transistors. An example is a method for semiconductor processing. An etch stop liner is formed in a semiconductor substrate. Forming the etch stop liner includes implanting etch selectivity dopants into the semiconductor substrate. The etch selectivity dopants form at least part of the etch stop liner. A source/drain cavity is formed in the semiconductor substrate. Forming the source/drain cavity includes etching the etch stop liner. Etching the etch stop liner selectively etches the etch stop liner relative to a material of the semiconductor substrate. A source/drain region is epitaxially grown in the source/drain cavity.

Abstract: A thin film transistor includes: a bottom gate electrode; a bottom gate electrode insulating layer, a semiconducting active layer and a first insulating layer which are disposed on the bottom gate electrode in sequence; a source electrode and a drain electrode which are disposed at a side of the first insulating layer away from the bottom gate electrode; vias disposed in the first insulating layer at positions which correspond to the source electrode and the drain electrode respectively; and ohmic contact layers disposed on and covering the semiconducting active layer at positions corresponding to the vias respectively. Each of the source electrode and the drain electrode is in contact with a corresponding one of the ohmic contact layers through a corresponding one of the vias.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a dielectric structure over a substrate. The integrated chip further includes a memory device having a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the plurality of lower interconnect layers. A sidewall spacer continuously extends from an outermost sidewall of the data storage structure to below an outermost sidewall of the bottom electrode.

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure. The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.

Abstract: Described is a micro-haptic actuator device that can be fabricated with roll-to-roll MEMS processing techniques. The device includes a first body having a first surface and a second, opposing surface, the body has a chamber defined by at least one interior wall, a piston member disposed in the chamber, physically spaced from the at least one interior wall of the chamber, the piston member having a first surface and a second opposing surface. A membrane layer is disposed over and attached to the first surface of the body, with a portion of the membrane attached to the first surface of the piston member. The device also includes a first electrode supported on a second surface the membrane, and a second body that supports a second electrode, with the second body attached to the second surface of the first body.

Abstract: A cooling apparatus for a power semiconductor includes a cooler having a cooling path so that a cooling medium flows therein, and an auxiliary cooling plate of a multi-layered structure joined to a surface of the cooler with which the power semiconductor comes into contact. A method of manufacturing the cooling apparatus includes providing an auxiliary cooling plate of a multi-layered structure, providing a cooler having a cooling path so that a cooling medium flows therein, and joining the auxiliary cooling plate to a surface of the cooler with which the power semiconductor comes into contact, wherein the providing a cooler and the joining the auxiliary cooling plate are performed together in the same brazing process, so that a manufacture of the cooler and the joining the auxiliary cooling plate are simultaneously performed.

Abstract: Provided are van der Waals (VDW) films comprising one or more transition metal chalcogenide (TMD) films. Also provided are methods of making VDW films. The methods are based on transfer of monolayer TMD films under vacuum, for example, using a handle layer. Also provided are apparatuses and devices comprising one or more VDW film.

Abstract: A display device including a light source including a first electrode having a light reflectance for a first light of greater than or equal to about 60%; an organic light emitting layer disposed on the first electrode and emitting the first light; and a second electrode disposed on the organic light emitting layer and having a light transmittance in a visible wavelength region of greater than or equal to about 70%, wherein the light source has a first absorption peak in a wavelength region of about 650 nanometers (nm) to about 750 nm or a second absorption peak in a wavelength region of about 550 nm to about 600 nm at a viewing angle of about 55 degrees to about 85 degrees, and a color filter layer disposed above the light source and including a quantum dot configured to convert the first light into a second light.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

Abstract: A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, where the second die is aligned to the first die with less than 800 nm alignment error, where the second die includes at least two second alignment marks positioned close to a second die edge of the second die, and where the third die is bonded to the first d

Abstract: An imaging device, includes: an imaging unit in which are disposed a plurality of pixels, each including a filter that is capable of changing a wavelength of light passing therethrough to a first wavelength and to a second wavelength and a light reception unit that receives light that has passed through the filter, and that captures an image via an optical system; an analysis unit that analyzes the image captured by the imaging unit; and a control unit that controls the wavelength of the light to be transmitted, by the filter based upon a result of analysis by the analysis unit.

Abstract: An organic light-emitting diode (OLED) display screen and an OLED display device are provided. The OLED display screen has a first display region, a second display region, and a folded display region. A bonding region is disposed on a side edge of the second display region away from the folded display region. Only part of a first backplate disposed on the second display region close to the bonding region is retained and replaced with a buffer layer to ensure stability of a shape of the folded display region and prevent wave warping.

Abstract: A semiconductor package includes a connection structure including a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a first connection via penetrating through the first insulating layer and connected to the first redistribution layer, a semiconductor chip disposed on the connection structure, an encapsulant covering at least a portion of the semiconductor chip, a second insulating layer disposed on the encapsulant, a second redistribution layer including a signal line disposed on the encapsulant, and a heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line.

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

Abstract: Methods of fabricating a structure for a metal-insulator-metal (MIM) capacitor. Conductive nanofibers are formed on a surface of a conductor layer. Each conductive nanofiber is terminated by an enlarged tip portion opposite the surface of the conductor layer. The enlarged tip portion is removed from each conductive nanofiber. The MIM capacitor may include the conductive nanofibers as portions of an electrode.

Abstract: A semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates.

Abstract: A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase.

Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a sapphire substrate preparation step S10 for preparing a sapphire substrate having, as a main surface, a {10-10} plane or a plane obtained by inclining the {10-10} plane at a predetermined angle in a predetermined direction; a heat treatment step S20 for performing a heat treatment over the sapphire substrate while performing a nitriding treatment or without performing the nitriding treatment; a buffer layer forming step S30 for forming a buffer layer over the main surface of the sapphire substrate after the heat treatment; and a growth step S40 for forming a group III nitride semiconductor layer, in which a growth surface has a predetermined plane orientation, over the buffer layer, in which at least one of a plane orientation of the main surface of the sapphire substrate, presence or absence of the nitriding treatment during the heat treatment, and a growth temperature in the buffer layer forming step is adjusted such that the

Abstract: Disclosed herein are a stretchable display panel and a stretchable device. The stretchable display panel comprises: a lower substrate having an active area and a non-active area surrounding the active area; a plurality of individual substrates disposed on the lower substrate, spaced apart from each other and located in the active area; a connection line electrically connecting a pad disposed on the individual substrate; a plurality of pixels disposed on the plurality of individual substrates; and an upper substrate disposed above the plurality of pixels, wherein the modulus of elasticity of the individual substrates is higher than that of at least one part of the lower substrate.