Patents Examined by Cathy F. Lam
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Patent number: 7332212Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: GrantFiled: October 5, 2005Date of Patent: February 19, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Patent number: 7332229Abstract: The invention provides a varnish that contains an insulting resin, a curing agent, a flame retardant, and an organic solvent. The flame retardant comprises flame retardant particles surface treated with at least one surface treatment agent selected from the group consisting of a phosphorus compound soluble in an organic solvent, an organosilicon compound and a dispersant having a carboxyl group. A formed material is obtained by applying and drying the varnish on a substrate. A multilayer structure is obtained by forming on a substrate having a conductor circuit layer an electrical insulation layer obtained by curing the formed material obtained from the varnish.Type: GrantFiled: April 15, 2003Date of Patent: February 19, 2008Assignee: Zeon CorporationInventors: Daisuke Uchida, Masafumi Kawasaki, Yasuhiro Wakizaka, Atsushi Tsukamoto
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Patent number: 7329817Abstract: The present invention provides a partially completed wiring circuit board assembly sheet capable of preventing deposition of a plating metal on the surface of a metal sheet, even when pinholes are produced in an insulating layer for insulating a lead wire for electroplating from a metal sheet. The assembly sheet 100 of the present invention has a metal sheet 1, multiple wiring circuit board forming area 1A in compartments on the metal sheet and area 1B for forming a lead wire for electroplating, which is in compartment on the metal sheet 1. Each area 1A has a partially completed wiring circuit board 10. The partially completed wiring circuit board 10 is equipped with a base insulating layer 2, a wiring pattern 3 and a cover insulating layer 4. In the area 1B, a first insulating layer 12, a lead wire 13 for electroplating and a second insulating layer 14 are laminated in this order. Of the metal sheet 1, an opening 16 is formed in the part under the lead wire 13.Type: GrantFiled: August 3, 2005Date of Patent: February 12, 2008Assignee: Nitto Denko CorporationInventors: Hidenori Aonuma, Tetsuya Ohsawa, Yasuhito Ohwaki
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Patent number: 7329458Abstract: Disclosed is a wiring member comprising a sheet-like porous substrate provided with a large number of open-cells which are three-dimensionally branched and opened to a first major surface as well as to a second major surface of the porous substrate, and a conductive portion formed on the first major surface of the porous substrate and formed at least partially an inter-penetrating structure together with the porous substrate at an interface of the porous substrate. The apertures of the open-cells on the first major surface have an average diameter and an average number of the apertures, at least one of which is smaller than that of the second major surface.Type: GrantFiled: October 29, 2003Date of Patent: February 12, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Toshiro Hiraoka, Yasuyuki Hotta, Shigeru Matake, Misa Sawanobori, Kou Yamada
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Patent number: 7326463Abstract: Circuit conductors and cables are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 50% of the weight of the conductive loaded resin-based material. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, aluminum fiber, or the like.Type: GrantFiled: February 14, 2005Date of Patent: February 5, 2008Assignee: Integral Technologies, Inc.Inventor: Thomas Aisenbrey
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Patent number: 7326460Abstract: A first conductive film is formed on a wiring pattern area on a plate by dropping liquid drops. A second conductive film which is electrically separated from the first conductive film is formed by discharging liquid drops outside of the wiring pattern area on the plate.Type: GrantFiled: March 24, 2004Date of Patent: February 5, 2008Assignee: Seiko Epson CorporationInventor: Toshimitsu Hirai
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Patent number: 7323238Abstract: In a printed board having a land as an electrode, a colored thermoplastic resin film is arranged on a land forming surface of a thermoplastic resin member so as to set a difference in light reflectivity between the land and the colored thermoplastic resin film, to be greater than that between the land and the thermoplastic resin member. An opening portion is provided in the colored thermoplastic resin film so that at least a part of the land is exposed from the opening portion. Because the colored thermoplastic resin film is positioned on the circumference portion of the opening portion, the difference in light reflectivity of the land with respect to its circumference portion can be effectively increased. As a result, a recognition ratio of the land can be effectively improved.Type: GrantFiled: September 22, 2005Date of Patent: January 29, 2008Assignees: DENSO Corporation, NEC Electronics CorporationInventors: Koji Kondo, Ryohei Kataoka, Tomohiro Yokochi, Makoto Nakagoshi, Tadashi Murai, Akimori Hayashi, Katsunobu Suzuki
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Patent number: 7323255Abstract: First, a melt of Al or a melt of an Al alloy containing Si is injected in a die filled with SiC powder and cast to form a plate member made of an Al/SiC composite. Next, an Al foil member made of an Al—Mg-based alloy is joined with the surface of the plate member through hot pressing. As a result, part of the Al foil member enters casting blowholes on the surface of the plate member to fill the casting blowholes. In addition, an Al—Mg-based alloy layer is formed on the surface of the plate member. Thus, a base plate having a nearly flat surface is produced.Type: GrantFiled: July 19, 2005Date of Patent: January 29, 2008Assignee: Kabushiki Kaisha Toyota JidoshokkiInventors: Katsufumi Tanaka, Kyoichi Kinoshita, Tomohei Sugiyama, Eiji Kono
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Patent number: 7323245Abstract: It comprises an electric conduction pattern member (11) which is flexible and plate-shaped, a gel member (13) having the electric conduction pattern member embedded therein, and flexible substrate sheets (15a, 15b) holding the gel member therebetween, the electric conduction pattern member (11) having the function of allowing the gel member (13) to be deformed and displaced by an external bending force, the stress due to the external bending force being dispersed by the gel member (13).Type: GrantFiled: March 19, 2004Date of Patent: January 29, 2008Assignee: Japan Aviation Electronics Industry, LimitedInventors: Tomishige Tai, Seiya Takahashi
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Patent number: 7324324Abstract: A multilayer electronic component is composed of a ceramic body obtained by laminating a plurality of ceramic layers via a conductor layer. The conductor layer is a plated film and extracted to one end face of the ceramic body, thereby contributing to the formation of capacity. A peripheral edge portion of the conductor layer composed of the plated film is thicker than its inner region. This avoids stripping on the peripheral edge portion of the conductor layer and avoids internal defects such as delamination. A dummy conductor layer may be formed at a distance on the end opposite the end face for extraction.Type: GrantFiled: March 24, 2005Date of Patent: January 29, 2008Assignee: Kyocera CorporationInventors: Koushiro Sugimoto, Katsuyoshi Yamaguchi, Yumiko Itoh
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Patent number: 7317258Abstract: An apparatus and system, as well as fabrication methods therefor, may include a unitary, substantially uniformly distributed transfer material coupled to a carrier material.Type: GrantFiled: March 6, 2006Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Rajen C. Dias, Yongmei Liu
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Patent number: 7312534Abstract: The present invention relates to interlayer dielectric materials and pre-applied die attach adhesives, more specifically pre-applied die attach adhesives (such as wafer and other substrate-applied die attach adhesives), methods of applying the interlayer dielectric materials onto substrates to prepare low K dielectric semiconductor chips, methods of applying the pre-applied die attach adhesives onto wafer and other substrate surfaces, and assemblies prepared therewith for connecting microelectronic circuitry.Type: GrantFiled: June 17, 2003Date of Patent: December 25, 2007Assignee: Henkel CorporationInventors: Benedicto delos Santos, James T. Huneke, Puwei Liu, Kang Yang, Qing Ji
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Patent number: 7306860Abstract: A layered structure includes a substrate comprising a layer of an oxide/oxide ceramic based composite material, a first oxide layer disposed directly on the substrate and formed from a material that has no greater than about 10% porosity and is substantially impermeable by water vapor, and a second oxide layer disposed directly on the first oxide layer and having a greater porosity than the first oxide layer. Either or both the first and second oxide layers of the coating system may be deposited using a plasma spraying process, a slurry deposition process which is followed by a sintering step, or an EB-PVD process.Type: GrantFiled: July 30, 2004Date of Patent: December 11, 2007Assignee: Honeywell International, Inc.Inventors: Thomas E. Strangman, Bjoern Schenk, Paul R. Yankowich
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Patent number: 7303639Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.Type: GrantFiled: August 22, 2005Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: Brian E. Curcio, Donald S. Farquhar, Lisa J. Jimarez, Keith P. Brodock
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Patent number: 7303698Abstract: A thick film composition consisting essentially of: a) electrically conductive powder; b) an inorganic binder wherein the inorganic binder is selected from TiO2 and any compounds that can generate TiO2 during firing and any one of the following compounds: Sb2O3, CO3O4, PbO, Fe2O3, SnO2, ZrO2, MnO, CuOx and mixtures thereof; and c) an organic medium.Type: GrantFiled: October 19, 2004Date of Patent: December 4, 2007Assignee: E.I. du Pont de Nemours and CompanyInventors: Yueli Wang, Christopher R. Needes, Patricia J. Ollivier
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Patent number: 7301097Abstract: A printed-circuit board includes a shield pattern layer that is stacked on a surface layer with respect to at least one wiring pattern layer that includes a wide-pattern area having a wiring width of more than 1 millimeter. Moreover, the shield pattern layer includes a shield pattern that is, from a plane view, overlapped on the wide-pattern area, and grounded without being electrically connected to an internal layer of other wiring pattern layers.Type: GrantFiled: December 22, 2004Date of Patent: November 27, 2007Assignee: Fujitsu LimitedInventors: Yoshiaki Hiratsuka, Yoshiro Tanaka
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Patent number: 7301228Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.Type: GrantFiled: December 3, 2003Date of Patent: November 27, 2007Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
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Patent number: 7297423Abstract: A PCB that can transmit a high frequency signal of a GHz band with a low loss includes an insulator and magnetic nanoparticles dispersed in the insulator.Type: GrantFiled: February 25, 2005Date of Patent: November 20, 2007Assignees: Sony Corporation, Migaku TakahashiInventors: Mikihisa Mizuno, Yuichi Sasaki, Makoto Inoue, Kenji Yazawa, Migaku Takahashi, Yasuo Tateno, Teiichi Miyauchi
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Patent number: 7294919Abstract: A device comprises a first substrate, a second substrate and a compliant element. The compliant element is composed of a first, compliant material between the first substrate and the second substrate and has a side surface coated at least in part with a layer of a second material. The compliant element exhibits deformation consistent with the first substrate and a second side having been pressed together. In some embodiments, the second material is electrically conductive such that the compliant element provides a reliable electrical connection between the substrates. In other embodiments, the second material increases the hermeticity of the compliant element such that the compliant element provides a better hermetic seal between the substrates.Type: GrantFiled: November 26, 2003Date of Patent: November 13, 2007Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventor: Qing Bai
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Patent number: 7294390Abstract: An improved electrical printed circuit exhibiting a combination of enhanced solderability and outstanding adhesion with a dielectric substrate includes a stack of two different types of conductive films. The stack includes a first conductive film that is printed onto the substrate with an ink that has been specially formulated to achieve enhanced adhesion with the substrate, and a second film that is applied over the first film using an ink that has been specifically formulated to achieve enhanced solderability.Type: GrantFiled: April 21, 2005Date of Patent: November 13, 2007Assignee: Delphi Technologies, Inc.Inventors: Bradley H. Carter, Lynda G. Flederbach, John K. Isenberg