Patents Examined by Cathy F. Lam
  • Patent number: 7294389
    Abstract: In a method of fabricating an array of microstructures, a substrate with an electrically-conductive portion is provided, an insulating mask layer is formed on the electrically-conductive portion of the substrate, a plurality of openings are formed in the insulating mask layer to expose the electrically-conductive portion, and a first plated or electrodeposited layer is deposited in the openings and on the insulating mask layer by electroplating or electrodeposition. A second plated layer is further formed on the first plated or electrodeposited layer and on the electrically-conductive portion by electroless plating to reduce a size distribution of microstructures over the array.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: November 13, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Teshima, Takayuki Yagi, Yasuhiro Shimada, Takashi Ushijima
  • Patent number: 7295421
    Abstract: A multilayer ceramic electronic component includes a skittered laminated body including internal electrodes that have a strength that is greater than that of ceramic layers provided therein. End portions of the internal electrodes protrude from end surfaces of the laminated body and are deformed so as to extend along the end surfaces by a barrel polishing process using balls. When external electrodes are formed on the end surfaces of the laminated body, a large contact area with the internal electrodes can be obtained. Therefore, a reliability of the electrical connection between the electrodes is definitely secured.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: November 13, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenjiro Mihara, Atsushi Kishimoto, Hideaki Niimi
  • Patent number: 7294393
    Abstract: In a sheet material (1), a bonding layer (2) is provided, and then a high-strength layer (3) is laminated on the bonding layer (2). The bonding layer (2) is made of an epoxy resin being a thermosetting material. The high-strength layer (3) is made of polyimide, which is not softened at a thermosetting temperature of the epoxy resin and has a tensile rupture strength higher than that of the cured thermosetting material. Moreover, the polyimide has a tensile rupture strength of 100 MPa or higher at 23° C. and a tensile rupture elongation of 10% or higher at 23° C. Assuming that a tensile rupture strength at ?65° C. is a and a tensile rupture strength at 150° C. is b, a ratio (a/b) is 2.5 or less.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: November 13, 2007
    Assignee: NEC Corporation
    Inventors: Hideya Murai, Tadanori Shimoto, Kazuhiro Baba, Katsumi Kikuchi
  • Patent number: 7291380
    Abstract: A method of plating a substrate including coating a substrate surface, laser-treating a region of the coated surface, and plating the region.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: November 6, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter S. Nyholm, Curt Lee Nelson, Niranjan Thirukkovalur, Paul McClelland
  • Patent number: 7288843
    Abstract: A substrate, in particular, a multilayer substrate, includes a mounting and electrical-connection support, and a face for mounting at least one integrated circuit chip (IC chip). The substrate and the mounted IC chip are placed in an injection mold. The injection mold has two parts that surround the periphery of the substrate. One part of the injection mold defines a cavity for molding an encapsulation material thereby encapsulating the IC chip, and includes a face for bearing on the mounting face. At least one recess is provided in one part of the injection mold. The recess defines, above the mounting face, a slot for providing a vent for venting gases. The mounting face includes a region on which a metal outer layer is placed. The metal outer layer extends along the recess and on the bearing face on both sides of the recess.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: October 30, 2007
    Assignee: STMicroelectronics SA
    Inventors: Christophe Prior, Laurent Herard
  • Patent number: 7288287
    Abstract: The insulating layer formation step of forming an insulating layer 24-1 on a base for resin application 20 by applying polymeric material, which has been diluted with a solvent, filled with inorganic filler to the base for resin application and by drying the base for resin application; the circuit formation portion forming step of creating a circuit formation portion and a via hole 25 in insulating layer 24-1 that has been formed in the above described insulating layer formation step by means of a laser treatment; and the circuit formation step of forming a circuit 23-1 by plating the circuit formation portion and via hole 25 that have been created in the above described circuit formation portion forming step are provided and the insulating layer formation step, the circuit formation portion forming step and the circuit formation step are repeated a plurality of times in this order and, thereby, a circuit formation part (multi-layered substrate) is manufactured.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: October 30, 2007
    Assignee: Omron Corporation
    Inventors: Hirokazu Tanaka, Satoshi Hirono
  • Patent number: 7289183
    Abstract: A copper conducting wire structure is for use in the thin-film-transistor liquid crystal display (LCD) device. The copper conducting wire structure includes at least a buffer layer and a copper layer. A fabricating method of the copper conducting wire structure includes the following steps. At first, a glass substrate is provided. Next, the buffer layer is formed on the glass substrate. The buffer layer is comprised of a copper nitride. At last, the copper layer is formed on the buffer layer.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: October 30, 2007
    Assignee: AU Optronics Corp.
    Inventors: Feng-Yuan Gan, Han-Tu Lin, Kuo-Yuan Tu
  • Patent number: 7285321
    Abstract: The present invention relates to a multi-layer laminate having a low glass transition temperature polyimide layer, a high glass transition temperature polyimide layer, and a conductive layer. The low glass transition temperature polyimide layer is synthesized by contacting an aromatic dianhydride with a diamine component, the diamine component comprising about 50 to about 90 mole % aliphatic diamine (the remainder being aromatic diamine) having the structural formula H2N—R—NH2 wherein R is hydrocarbon from C4 to C16. The low glass transition polyimide is an adhesive and has a glass transition temperature in the range of from 150° C. to 200° C. The high glass transition temperature polyimide layer has a glass transition temperature above the low glass transition temperature polyimide layer and is a thermoset polyimide.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 23, 2007
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Kuppsuamy Kanakarajan, Brian C. Auman, Sounak Banerji
  • Patent number: 7285316
    Abstract: The present invention is directed to a process for the manufacture of three-dimensional acoustically sound automotive insulation parts. In particular, the process includes mixing a two component polyurethane resin, applying the resin to a substrate, molding the substrate and then trimming and demolding the resin applied substrate.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: October 23, 2007
    Assignees: Bayer MaterialScience LLC, Bayer Aktiengesellschaft
    Inventors: Sven Meyer-Ahrens, Thomas J. Matwiczyk, Bin Lee, Michael A. Blaszkiewicz, Walter Guarnieri
  • Patent number: 7279217
    Abstract: There is provided a multilayer ceramic device enabling achievement of secure electric connection via electroconductive members in through holes and reduction in the thickness of internal electrodes during manufacturing. In multilayer piezoelectric device 1, a melting point of a material of the electroconductive members in the through holes is higher than a melting point of a material of the internal electrodes 2 and others. For this reason, the electroconductive members in the through holes have a contraction percentage in baking smaller than that of the internal electrodes 2 and others. Therefore, contraction of the electroconductive members is relatively constricted in baking, so as to decrease the difference of contraction percentages in baking between green sheets intended for piezoelectric layers 3 and others, and the electroconductive members in the through holes. This results in preventing breakage of the electrical connection via the electroconductive members in the through holes.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: October 9, 2007
    Assignee: TDK Corporation
    Inventor: Satoshi Sasaki
  • Patent number: 7267713
    Abstract: Provided is a conductive paste capable of adjusting resistivity and forming a conductor film having high strength of bonding with a glass substrate and high mounting strength of a metal terminal. The conductive paste contains a conductive component, a glass frit having a composition containing a Bi2O3—B2O3—SiO2—Al2O3 or Bi2O3—B2O3—SiO2—Al2O3—ZnO primary component and about 0.5 to 5% by weight of NiO as a secondary component, and an organic vehicle. The conductive paste is applied on a glass substrate and then baked to form a conductor film. A glass circuit structure formed by using the conductor film can be advantageously used as a defogging glass for an automobile window.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Fumiya Adachi
  • Patent number: 7265803
    Abstract: A circuit sheet comprising a substrate and wells dispersed on the substrate operable to hold conductive polymers that form circuit devices.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: September 4, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Gregory Frank Carlson, Todd Alan McClelland, Patrick Alan McKinley
  • Patent number: 7265298
    Abstract: A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: September 4, 2007
    Assignee: The Regents of the University of California
    Inventors: Mariam N. Maghribi, Peter A. Krulevitch, Thomas S. Wilson, Julie K. Hamilton, Christina Park
  • Patent number: 7264482
    Abstract: An anisotropic conductive sheet capable of transmitting high-speed digital signals reliably is provided. The anisotropic conductive sheet has a conductive property in a thickness direction thereof under a predetermined condition, and includes: insulative matrix members having a dielectric constant value of at most 2.28 and a dielectric loss value of at most 0.025; and conductive members having a conductive property in the thickness direction under the predetermined condition in the conductive members capable of flowing electricity between top and bottom surfaces thereof are located in a scattered manner in the matrix members, and the conductive and matrix members are bonded chemically. Especially, the matrix member is made from a resin material having a resin foamed body of a foaming structure, i.e. homogeneous microcell structure. At least one of the conductive members may be of conductive elastomer.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: September 4, 2007
    Assignee: J.S.T. Mfg. Co., Ltd.
    Inventor: Miki Hasegawa
  • Patent number: 7261841
    Abstract: A thick film composition consisting essentially of: a) electrically conductive powder; b) an inorganic binder wherein the inorganic binder is selected from TiO2 and any compounds that can generate TiO2 during firing; and c) an organic medium.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: August 28, 2007
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Yueli Wang, Christopher R. Needes, Patricia J. Ollivier
  • Patent number: 7255919
    Abstract: Provision of a releasing layer transfer film which can form, in a simple manner, a releasing layer on a COF flexible printed wiring board, the releasing layer preventing melt adhesion of an insulating layer to a heating tool, thereby enhancing productivity and reliability of semiconductor devices produced by use of a semiconductor chip mounting line. The releasing layer transfer film 1 for forming a releasing layer onto an insulating layer serving as a component layer of a COF flexible printed wiring board, the releasing layer transfer film includes a transfer film substrate 2 and a transferable releasing layer 3 provided on a surface of the transfer film substrate 2, wherein the transferable releasing layer 3 is formed from a releasing agent and can be transferred onto the insulating layer.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: August 14, 2007
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Ken Sakata, Katsuhiko Hayashi
  • Patent number: 7252891
    Abstract: A wiring transfer sheet including a carrier base and a wiring layer formed thereon is produced so that an exposed area of a surface of the carrier base on which the wiring layer is formed has a plurality of concavities. By transferring the wiring layer to an electrically insulating substrate with this wiring transfer sheet, convexities which are complementary to the concavities are formed on the electrically insulating substrate. The convexities improve adhesion between a wiring board and a resin stacked thereon. Therefore, the wiring board thus obtained has surface coplanarity suitable for mounting a semiconductor bare chip and an electronic component as a whole, and a microscopical surface structure which adheres to a material stacked thereon.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: August 7, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideki Higashitani
  • Patent number: 7250840
    Abstract: A layered product prepared by applying a surface treatment to an adherend having a surface with a low binding property with an anaerobic adhesive, which does not require a complex work, primer application, effected by accelerating an adhesive curing rate, and does not change surface conditions of the adherend. The layered product comprises an adherend, an uneven deposition comprising Cu, V, a Cu alloy or a V alloy and having a height of 500 nm or less on the surface of the adherend, and an adhesive layer formed at least on the uneven deposition.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: July 31, 2007
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Ryo Osugi
  • Patent number: 7243951
    Abstract: Durable security devices that are resistant to chemical attack and mechanical degradation and security articles employing such devices, are provided. By way of the durable security device of the present invention, opposing longitudinal borders adjacent an information-bearing layer are sealed, thereby preventing corrosive and/or degrading materials from reaching this layer through these sealed borders. In a preferred embodiment, at least a portion of the information-bearing layer is fully encapsulated, thereby rendering this portion or layer and the information conveyed thereby, impervious to chemical attack.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: July 17, 2007
    Assignee: Technical Graphics, Inc.
    Inventors: Paul F. Cote, Stephen B. Curdo, Gerald J. Gartner, Daniel G. Leeds, Brian C. Page, Gary R. Wolpert, Timothy T. Crane
  • Patent number: 7241510
    Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 10, 2007
    Assignee: Motorola, Inc.
    Inventors: Gregory J. Dunn, Remy J. Chelini, Timothy B. Dean