Patents Examined by Cathy Lam
  • Patent number: 7728232
    Abstract: An exemplary adhesive layer includes an adhesive main body having a first adhesive surface and a second adhesive surface on an opposite side of the adhesive main body to the first adhesive surface. The adhesive main body defines a number of through-holes between the first adhesive surface and the second adhesive surface therein. The through-holes are filled with an inner adhesive that has a higher adhesion than the adhesive main body. Adhesiveness of the first adhesive surface and the second adhesive surface of the adhesive main body can be improved, thereby preventing a printed circuit board having the adhesive layer from distortion.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 1, 2010
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Foxconn Advanced Technology Inc.
    Inventors: Feng-Yan Huang, Shing-Tza Liou
  • Patent number: 7722950
    Abstract: An adhesive for a circuit material, comprises a blend of a cure system; and a solid epoxy resin and a nitrile rubber functionalized with epoxy-reactive groups, wherein the solid epoxy resin and the nitrile rubber are reacted to form an adduct prior to blending with the cure system. The adhesive has low dendritic growth and improved solder resistance.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 25, 2010
    Assignee: World Properties, Inc.
    Inventors: David Guo, Carlos L. Barton
  • Patent number: 7723855
    Abstract: A pad for soldering a contact of a surface mounted component is provided herein. The pad includes a central portion and a plurality of separate extending portions extending from the central portion. All of the plurality of separate extending portions includes a free end and a connected end connected to the central portion. A width of the free end is larger than a width of the connected end. A circuit board and an electronic device are also provided.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: May 25, 2010
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Shu-Jen Tsai, Long-Fong Chen, Wen-Haw Tseng, Shih-Fang Wong
  • Patent number: 7718273
    Abstract: The present invention provides a wiring material for forming wiring on a substrate by causing coalescence of conductive particles through heating, and including a binder layer and a wiring layer. The binder layer contains metal particles and having a binder function to be adhered to the substrate; and the wiring layer contains metal particles and laminated on the binder layer. The metal particles of the binder layer and the metal particles of the wiring layer are in contact with each other. With this arrangement, it is possible to provide a wiring material allowing use of a larger variety of materials, while also ensuring low resistance of wiring and improvement of adhesion between the wiring and the substrate.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 18, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akiyoshi Fujii, Toshio Tahira, Nobukazu Nagae
  • Patent number: 7705471
    Abstract: A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 27, 2010
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Wen-Hung Hu
  • Patent number: 7691469
    Abstract: A ceramic multilayer substrate exhibiting reduced pealing and breakage of an internal conductor disposed between a ceramic layer serving as a base member and a ceramic layer for restricting shrinkage includes a first ceramic layer 11, a second ceramic layer 12 laminated so as to come into contact with a principal surface of the first ceramic layer 11, and an internal conductor 13 disposed between the first ceramic layer 11 and the second ceramic layer 12, a phosphorus component layer 16a is disposed in the first ceramic layer 11 with a concentration gradient in which the concentration decreases in a direction away from the internal conductor 13.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: April 6, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masato Nomiya
  • Patent number: 7691458
    Abstract: Numerous embodiments of a carrier substrate having thermochromatic materials are described. In one embodiment of the present invention, a carrier substrate has a visible surface, and a thermochromatic material is disposed near the carrier substrate. The thermochromatic material produces a visual change of the visible surface when an activation temperature of the thermochromatic material is reached.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Patrick D. Boyd
  • Patent number: 7687137
    Abstract: There is provided a dimensionally accurate insulating substrate in which plane direction-wise shrinkage is practically zero and shrinkage variations are small. The insulating substrate includes a laminated body composed of at least two kinds of insulating layers made of crystallizable glass ceramics. The crystallization temperature of crystallizable glass contained in the first insulating layer is lower than the softening point of crystallizable glass contained in the second insulating layer. The difference in thermal expansion coefficient between the first and second insulating layers is preferably 2×10?6/° C. or below.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 30, 2010
    Assignee: Kyocera Corporation
    Inventors: Tatsuji Furuse, Seiichiro Hirahara, Sentarou Yamamoto, Kouji Yamamoto, Mitsugi Ogawauchi, Satoru Kajihara
  • Patent number: 7681991
    Abstract: A composite ceramic substrate for receiving an ejection head chip for a micro-fluid ejection head and a method for making the composite ceramic substrate. The substrate includes a high temperature previously fired ceramic base having a substantially planarized first surface and at least one fluid supply slot therethrough. A low temperature co-fired ceramic (LTCC) tape layer bundle having at least two LTCC tape layers is attached to the ceramic base at an interface between the LTCC tape layer bundle and the first surface of the ceramic base. The LTTC tape layer bundle has at least one chip pocket therein and at least one of the LTCC tape layers includes a plurality of conductors.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: March 23, 2010
    Assignee: Lexmark International, Inc.
    Inventors: Frank Edward Anderson, Michael John Dixon, Eric Spencer Hall, Elios Klemo, Bryan Dale McKinley, Jeanne Marie Saldanha Singh
  • Patent number: 7674984
    Abstract: In order to prevent stress caused by bending a flexible wiring board from being applied to the connection section between the flexible wiring board and a driving IC, solder is deposited as a reinforcement member, on both sides of the driving IC connected onto the flexible wiring board.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: March 9, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tomoyuki Kubo
  • Patent number: 7670672
    Abstract: In a multilayer ceramic substrate having a cavity, base-material layers are arranged on a base side with respect to an interface between the base and a wall defining a cavity, and a constraining interlayer is arranged on the wall side. A conductive film is arranged between the base-material layers and the constraining interlayer, the base-material layers and the constraining interlayer sandwiching the interface. The effect of the first conductive film results in an increase in the adhesion of the constraining interlayer to the substrate layers, thus enhancing a shrinkage-inhibiting effect of the constraining interlayer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: March 2, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuichi Iida
  • Patent number: 7667142
    Abstract: Prepregs, laminates, printed wiring board structures and processes for constructing materials and printed wiring boards that enable the construction of printed wiring boards with improved thermal properties. In one embodiment, the prepregs include substrates impregnated with electrically and thermally conductive resins. In other embodiments, the prepregs have substrate materials that include carbon. In other embodiments, the prepregs include substrates impregnated with thermally conductive resins. In other embodiments, the printed wiring board structures include electrically and thermally conductive laminates that can act as ground and/or power planes.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: February 23, 2010
    Assignee: Stablcor, Inc.
    Inventors: Kalu K. Vasoya, Bharat M. Mangrolia, William E. Davis, Richard A. Bohner
  • Patent number: 7658988
    Abstract: Compositions and processes for the preparation of printed circuits from epoxy compositions are provided. The epoxy compositions exhibit low viscosity in the uncured state and low coefficient of thermal expansion in the cured state. The low dielectric constant compositions of the invention are well-suited for use in multi-layer printed circuit boards.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: February 9, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
  • Patent number: 7655871
    Abstract: A multiple-layered printed wiring board is manufactured, which exhibits higher thermal resistance and lower thermal expansion so that no flaking and/or no crack would be occurred in a thermal shock test such as a cooling-heating cycle test and the like, in addition to exhibiting a fire retardancy.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: February 2, 2010
    Assignee: Sumitomo Bakelite Company Limited
    Inventors: Masataka Arai, Takeshi Hosomi, Hiroaki Wakabayashi
  • Patent number: 7655292
    Abstract: An electrically conductive substrate with a high heat conductivity has an aluminum plate having multiple holes. An isolation layer is formed on the aluminum plate and inner walls of the holes. Multiple electrically conductive materials are inserted in the holes. A circuit layer is formed on the aluminum plate, electrically connects to the electrically conductive materials and has a rough surface. A graphite layer is formed on the rough surface of the circuit layer. The electric components are respectively provided on the holes, and the heat generated by the electric components is dissipated effectively by the aluminum plate.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: February 2, 2010
    Assignee: Kaylu Industrial Corporation
    Inventor: Li-Wei Kuo
  • Patent number: 7642466
    Abstract: There is provided a configuration in which rigid substrates are connected via flexible substrates, the connection configuration having a pair of rigid substrates each having a predetermined circuit pattern on a front and a reverse surface thereof, a first flexible substrate attached on the front surfaces of the pair of the rigid substrates so as to electrically connect the circuit patterns provided respectively on the front surfaces, a second flexible substrate attached on the reverse surfaces of the pair of the rigid substrates so as to electrically connect the circuit patterns provided respectively on the reverse surfaces. The first and the second substrate have a gap therebetween smaller than a thickness of the pair of the rigid substrates.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: January 5, 2010
    Assignee: Fujikura Ltd.
    Inventors: Shinichi Nikaido, Hiroki Maruo
  • Patent number: 7638873
    Abstract: A wired circuit board is provided which can reduce transmission loss with a simple layer structure and also features excellent long-term reliability by preventing the occurrence of an ion migration phenomenon between a metal foil and an insulating layer to improve the adhesion between the metal foil and the insulating layer and the conductivity of a conductor. A metal supporting board is prepared and a first metal thin film is formed on the metal supporting board by sputtering or electrolytic plating. A metal foil is formed on the first metal thin film by electrolytic plating. A second metal thin film is formed over the metal foil and the metal supporting board by electroless plating or sputtering. An insulating base layer is formed on the second metal thin film. A conductive pattern is formed as a wired circuit pattern on the insulating base layer. An insulating cover layer is formed on the insulating base layer to cover the conductive pattern.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: December 29, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Jun Ishii, Yasuhito Funada
  • Patent number: 7635815
    Abstract: Prepregs, laminates, printed wiring board structures and processes for constructing materials and printed wiring boards that enable the construction of printed wiring boards with improved thermal properties. In one embodiment, the prepregs include substrates impregnated with electrically and thermally conductive resins. In other embodiments, the prepregs have substrate materials that include carbon. In other embodiments, the prepregs include substrates impregnated with thermally conductive resins. In other embodiments, the printed wiring board structures include electrically and thermally conductive laminates that can act as ground and/or power planes.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: December 22, 2009
    Assignee: Stablcor, Inc.
    Inventors: Kalu K. Vasoya, Bharat M. Mangrolia, William E. Davis, Richard A. Bohner
  • Patent number: 7629045
    Abstract: The invention relates to an adhesion assisting agent-bearing metal foil comprising a layer of an adhesion assisting agent containing an epoxy resin as an indispensable component on a metal, wherein the adhesion assisting agent layer has a thickness of 0.1 to 10 ?m. The invention also relates to a printed wiring board being a multilayer wiring board having a plurality of layers, wherein an adhesion assisting agent layer is formed between insulating layers.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: December 8, 2009
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Takako Watanabe, Shin Takanezawa, Koji Morita, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Patent number: 7626128
    Abstract: A conductive film has transparency and a high level of electrical conductivity, which is used for an electromagnetic interference film hardly causing a moiré phenomenon, and the like. To achieve the above-mentioned aim, the following disclosure is disclosed. A conductive film in which a conductive portion of a random network structure is present on at least one surface of a base film, a line width of the conductive portion composing the network structure is 30 ?m or less, an area of portions where the conductive portion is not present is 50% or more with respect to an area of the conductive film, and an average of ratios of a major axis length to a minor axis length of an area surrounded by the network of the conductive portion, in which the base film is exposed, is larger than 1 and is equal to or less than 3.5.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: December 1, 2009
    Assignee: Toray Industries, Inc.
    Inventors: Yasushi Takada, Shotaro Tanaka, Junpei Ohashi