Patents Examined by Cathy Lam
  • Patent number: 7622806
    Abstract: A laser mark is inscribed on an IC component, which character stroke consists of a plurality of laser paths inscribed by a laser beam. The width of the character stroke is greater than the widths of the laser paths. In addition, at least two of the laser paths, moving in opposite directions or in a same direction of the laser beam, are integrally connected as a laser-inscribing stroke to reduce end-to-end breaks between the laser paths.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: November 24, 2009
    Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.
    Inventors: Shu-Ling Su, A-Tsung Cheng
  • Patent number: 7622183
    Abstract: The present invention provides a multilayer printed wiring board having a filled viahole structure advantageously usable for forming a fine circuit pattern thereon, and having an excellent resistance against cracking under a thermal shock or due to heat cycle. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers each having formed through them holes each filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 ?m.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 24, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Seiji Shirai, Kenichi Shimada, Motoo Asai
  • Patent number: 7615277
    Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 10, 2009
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Katsuyuki Masuda, Kiyoshi Hasegawa
  • Patent number: 7615705
    Abstract: A printed circuit board is fabricated so contacts for tight-pitch components are at an angle with respect to the bundles of glass fibers in the epoxy-glass printed circuit board such that adjacent component contacts do not contact the same bundle of glass fibers. This angle may be accomplished by manufacturing a printed circuit board panel with the glass fibers at an angle with respect to its edges. This angle may also be accomplished by placing parts on a printed circuit board panel that has a traditional X-Y orthogonal weave of glass fiber bundles at an angle with respect to the edges of the panel. This angle may also be accomplished by starting with a traditional panel that has an X-Y orthogonal weave, laying out parts on the panel along the X-Y weave, then placing components on the parts at an angle with respect to the edges of the parts.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Bruce John Chamberlin, Mitchell G. Ferrill, Roger Scott Krabbenhoft
  • Patent number: 7608929
    Abstract: An electrical connector structure of circuit board and a method for fabricating the same are proposed. A circuit board having a conductive layer is formed with a first resist layer and a second resist layer thereon, so as to form electrical connection pads and metal bumps on the electrical connection pads. The first and second resist layers are formed with openings therein at positions corresponding to the electrical connection pads and metal bumps, and the exposed conductive layer is removed. An adhesive layer is formed to cover the exposed surfaces of the electrical connection pads and the metal bumps. Then, the second resist layer, the first resist layer and the conductive layer covered by the first resist layer are removed. Later, an insulating protective layer is formed on a surface of the circuit board, and thinned to expose a portion of the adhesive layer, such that electrical connectors of the circuit board are fabricated.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 27, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Wen-Hung Hu
  • Patent number: 7601419
    Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: October 13, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Seok Song, Taehoon Kim
  • Patent number: 7595997
    Abstract: In a multilayer ceramic electronic component, a pedestal portion is provided on a region of a first main surface of a multilayer ceramic body and includes a non-metallic inorganic powder and a resin so that the pedestal portion is fixed to the first main surface with at least the resin, the multilayer ceramic body being formed by stacking a ceramic base material layer and a shrinkage-inhibiting layer having a predetermined conductor pattern. Also, a via hole conductor is disposed in the pedestal portion so that one of the end surfaces is exposed in a surface of the pedestal portion, and a surface mounting-type electronic component such as a semiconductor element is connected, through a conductive binder, to the one of the end surfaces of the via hole conductor exposed in the surface of the pedestal portion. A resin is provided between the surface mounting-type electronic component and the pedestal portion, the resin having the same composition as in the resin of the pedestal portion.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: September 29, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masato Nomiya, Norio Sakai, Mitsuyoshi Nishide
  • Patent number: 7586047
    Abstract: An object of the present invention is to provide a method for manufacturing a porous material in which complicated and fine through portions, recessed portions, and the like have been patterned. It is to provide a patterned porous molded product or nonwoven fabric, in which a plated layer has been selectively formed on the surfaces of the through portions and the recessed portions. With the invention, a mask having through portions in a pattern is placed on at least one side of the porous molded product or the nonwoven fabric. A fluid or a fluid containing abrasive grains is sprayed from above the mask, thereby to form through portions or recessed portions, or both of them, to which the opening shape of each through portion of the mask has been transferred, in the porous molded product or the nonwoven fabric.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: September 8, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumihiro Hayashi, Yasuhito Masuda, Yasuhiro Okuda
  • Patent number: 7572500
    Abstract: A conductive portion is formed in a hole formed in a material sheet. A metal foil is placed on a surface of the material sheet to provide a laminated sheet. The laminated sheet is heated and pressed to provide a circuit-forming board. The metal foil includes a pressure absorption portion and a hard portion adjacent to the pressure absorption portion. The pressure absorption portion has a thickness changing according to a pressure applied thereto. The circuit-forming board provided by this method provides a high-density circuit board of high quality having reliable electrical connection.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: August 11, 2009
    Assignee: Panasonic Corporation
    Inventor: Toshihiro Nishii
  • Patent number: 7572503
    Abstract: Directed to an insulating resin composition which comprises (A) a novolak epoxy resin having a biphenyl structure, (B) carboxylic acid-modified acrylonitrile butadiene rubber particles, (C) a triazine ring-containing cresol novolak phenolic resin, (D) a phenolic hydroxyl group-containing phosphorus compound, and (E) inorganic filler, an insulating film having a support using the same, a multilayer wiring board, and a process for producing a multilayer wiring board.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: August 11, 2009
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Shin Takanezawa, Koji Morita, Takako Watanabe, Toshihisa Kumakura, Hiroyuki Fukai, Hiroaki Fujita
  • Patent number: 7556850
    Abstract: A wiring circuit board at least contains an electric insulator layer and an electric conductor formed on the electric insulator layer so as to form a predetermined circuit pattern, which further comprises an adhesive layer formed by thermal hardening of the thermosetting adhesive and pressure-sensitive adhesive composition as described in the specification.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: July 7, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Miyoko Ikishima, Masahiro Ooura
  • Patent number: 7557302
    Abstract: A printed circuit board for preventing electrostatic discharge damage includes several electronic components thereon. The printed circuit board defines a number of through holes therein. The printed circuit board includes a signal layer. The signal layer defines a first copper foil and second copper foil thereon. The first copper foils are disposed around the corresponding through holes and connect with the through holes. The second copper foils are disposed around the first copper foils and extend to two adjacent edges of the printed circuit board. The first copper foil and the second copper foil have a number of saw teeth. A gap between the first copper foil and the second foil is in the range from 0.1-0.125 mm.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: July 7, 2009
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hong Hai Precision Industry Co., Ltd.
    Inventor: Yu-Xiang Wang
  • Patent number: 7558047
    Abstract: An electronic component is provided which includes external electrodes having a multilayer structure of first and second sintered electrode layers that are densely sintered and have less possibility of causing poor appearance and decreased reliability in electrical connection. Each external electrode includes a first sintered electrode layer and a second sintered electrode layer. The first sintered electrode layer contains a first borosilicate glass containing an alkali metal in which there is 85% to 95% by weight of silicon and 0.5% to 1.5% by weight of the alkali metal based on 100% by weight of all contained elements other than boron. The second sintered electrode layer contains a second borosilicate glass containing an alkali metal in which there is 65% to 80% by weight of silicon and 3.5% to 8.0% by weight of the alkali metal based on 100% by weight of all contained elements other than boron.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: July 7, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuji Ukuma
  • Patent number: 7550825
    Abstract: The present invention relates to interlayer dielectric materials and pre-applied die attach adhesives, more specifically pre-applied die attach adhesives (such as wafer and other substrate-applied die attach adhesives), methods of applying the interlayer dielectric materials onto substrates to prepare low K dielectric semiconductor chips, methods of applying the pre-applied die attach adhesives onto wafer and other substrate surfaces, and assemblies prepared therewith for connecting microelectronic circuitry.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: June 23, 2009
    Assignee: Henkel Corporation
    Inventors: Benedicto delos Santos, James T. Huneke, Puwei Liu, Kang Yang, Qing Ji
  • Patent number: 7547849
    Abstract: A light-activatable polymer composition and polymer composite includes a polymer binder selected from epoxy resins, silica filled epoxy, bismaleimide resins, bismaleimide triazines, fluoropolymers, polyesters, polyphenylene oxide/polyphenylene ether resins, polybutadiene/polyisoprene crosslinkable resins (and copolymers), liquid crystal polymers, polyamides, cyanate esters, or combinations thereof, the polymer binder being present in an amount from 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 96, or 97 weight-percent of the total weight of the polymer composition; a spinel crystal filler present in an amount from 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55 and 60 weight-percent of the total weight of the polymer composition, and methods for making same are provided.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: June 16, 2009
    Assignee: E.I. Du Pont de Nemours and Company
    Inventors: Yueh-Ling Lee, Meredith L. Dunbar, Harry Richard Zwicker, Carl B. Wang, Brian C. Auman, Shane Fang
  • Patent number: 7547479
    Abstract: A coated article, which contains (i) at least one electrically non-conductive base layer, (ii) at least one layer of copper and/or a copper alloy, and (iii) a tin-containing layer, wherein the layer (ii) is positioned between the layer (i) and the layer (iii). The article is characterized in that the tin-containing layer (iii) contains at least one other metal.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: June 16, 2009
    Assignee: Ormecon GmbH
    Inventor: Bernhard Wessling
  • Patent number: 7538440
    Abstract: A printed circuit board having at least one conductive region covered in solder paste has preformed solder elements placed on the solder paste in the conductive region. A component package is placed onto the printed circuit board over the conductive region and the solder is reflowed, forming a wide solder interconnection between the component and the conductive region of the printed circuit board.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Dudi I. Amir, Damion T. Searls
  • Patent number: 7535715
    Abstract: A conformable paste comprising porous agglomerates of carbon black dispersed in a paste-forming vehicle is disclosed. The paste is useful as an interface material for improving the thermal contact between two proximate solid surfaces, such as the surfaces of a heat source and a heat sink. Upon compression between the two solid surfaces, the paste forms a material that enhances the thermal contact between said surfaces. This invention also discloses a conformable interface material which, upon compression between two proximate solid surfaces, forms a material that enhances the thermal contact between said surfaces. This interface material comprises (i) a sheet and (ii) a conformable, spreadable and thermally conductive paste on each of the two opposite sides of the sheet, said paste comprising porous agglomerates of carbon black dispersed in a paste-forming vehicle. In addition, a method of providing a thermal contact between two solid surfaces is disclosed.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 19, 2009
    Inventor: Deborah Duen Ling Chung
  • Patent number: 7531204
    Abstract: A light-activatable polymer composition and polymer composite includes a polymer binder selected from epoxy resins, silica filled epoxy, bismaleimide resins, bismaleimide triazines, fluoropolymers, polyesters, polyphenylene oxide/polyphenylene ether resins, polybutadiene/polyisoprene crosslinkable resins (and copolymers), liquid crystal polymers, polyamides, cyanate esters, or combinations thereof, the polymer binder being present in an amount from 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 96, or 97 weight-percent of the total weight of the polymer composition; a spinel crystal filler present in an amount from 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 20, 25, 30, 35, 40, 45, 50, 55 and 60 weight-percent of the total weight of the polymer composition, and methods for making same are provided.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: May 12, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Yueh-Ling Lee, Meredith L. Dunbar, Harry Richard Zwicker, Carl B. Wang, Brian C. Auman, Shane Fang
  • Patent number: RE40947
    Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: October 27, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Kenichi Shimada, Kouta Noda, Takashi Kariya, Hiroshi Segawa