Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.

Abstract: LED apparatuses featuring etched mesas and techniques for manufacturing LED apparatuses are described, including techniques for reducing surface recombination and techniques for charge carrier confinement. Etched facets of an LED mesa can be passivated using epitaxial regrowth of one or more semiconductor regrowth layers. The one or more semiconductor regrowth layers can include a transition layer. The transition layer can be configured with a bandgap energy between that of layers that are on opposite sides of the transition layer. A transition layer can separate an etched facet and another regrowth layer or separate two regrowth layers. In some instances, selective etching can be performed to preferentially etch a quantum well layer relative to a barrier layer. The selective etching removes surface imperfections, which contribute to surface recombination and which tend to be more prevalent in etched facets of the quantum well layer than etched facets of the barrier layer.

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

Abstract: A substrate and a manufacturing method therefor, and an electronic device are provided. The substrate includes: a base substrate including a working region, and a non-working region outside of the working region, the non-working region including a peripheral circuit region near the working region and a non-circuit region away from the working region; a peripheral circuit in the peripheral circuit region; a common electrode lead in the non-working region; a common electrode; and a bridging conductive layer made of opaque conductive material in the non-working region and electrically connects the common electrode and the common electrode lead. An orthographic projection of the bridging conductive layer on the base substrate at least partially coincides with an orthographic projection of the peripheral circuit region on the base substrate, and bridging conductive layer is insulated from the peripheral circuit.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

Abstract: A light-emitting device includes a plurality of light-emitting diodes, a first cured composition over a first subset of the light-emitting diodes, and a second cured composition over a second subset of light-emitting diodes. The first cured composition includes a first photopolymer and a blue photoluminescent material that is an organic, organometallic, or polymeric material, embedded in the first photopolymer. The second cured composition includes a second photopolymer and a nanomaterial embedded in the second photopolymer. The nanomaterial is selected to emit red or green light in response.

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple channel structures suspended over a semiconductor substrate. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the channel structures. The semiconductor device structure further includes a gate stack wrapping around the channel structures. In addition, the semiconductor device structure includes a conductive contact wrapping around terminals of the epitaxial structures.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: A high-power light-emitting diode is made by monolithically integrating multiple miniature light-emitting chips for improved operation voltage, light extraction efficiency and device yield. The light emitting diode includes a plurality of monolithically integrated mini chips, each of the mini chips has a mini n-contact formed on an n-type structure, a mini p-ohmic contact formed on a p-type structure, and a mini light emitting area defined by the mini p-ohmic contact. An n-bridge metal electrically connecting the mini n-contact of the mini chips to an n-bonding pad, the n-bridge metal is formed on the p-type structure and on sidewall of an opening in the p-type structure and on the active-region.

Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

Abstract: The present application discloses a display panel, a display device and a manufacturing method. The display panel includes light-emitting diodes. The light-emitting diodes includes a blue luminescent layer. The blue luminescent layer includes a germanium silicon quantum dot material. A proportion range of a silicon element in the light-emitting diodes is 65%-90%, and a proportion range of a germanium element is 10%-35%.

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.