Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: An Electro-Static-Discharge (ESD) protection circuit has a Silicon-Controlled Rectifier (SCR) with a discharge current path in a first direction. A triggering transistor has a trigger current flowing in a second direction that is perpendicular to the first direction. Triggering transistors can be Fin Field-Effect Transistor (FinFET) transistors with current flowing along the long direction of the fins. The trigger current flows into a connecting N+ drain and into an N-Well under a center portion of the connecting N+ drain to inject carriers into the N-base of a PNPN SCR. The injected current flows through the base to generate a voltage gradient that turns on the PN junction in a P+ emitter that is parallel to but spaced apart from the FinFET transistors, causing a discharge current to flow perpendicular to the fins. The perpendicular discharge current flows through the substrate which can handle a larger current than the small fins.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures and a gate structure across the fin structures. The gate structure includes a gate dielectric layer over fin structures, a work function layer over the gate dielectric layer, and a contact layer over the work function layer. In some embodiments, a portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A method for forming a semiconductor structure is also provided.

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Abstract: A semiconductor device according to the present disclosure includes a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure, and a second field effect transistor having a Fin structure, in which the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor.

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

Abstract: A gate-all-around (GAA) semiconductor device structure and method for forming the same. The GAA structure includes a nanosheet stack disposed over a patterned portion of a substrate, and an encapsulation structure surrounding the patterned portion of the substrate underlying the nanosheet stack. The method for forming the GAA structure includes forming a liner over and in contact with a nanosheet fin, a sacrificial layer disposed below the nanosheet fin, and a patterned portion of a substrate underlying the nanosheet fin. At least one portion of the liner is etched down to the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the nanosheet fin and the patterned portion of the substrate. An insulting layer is formed within the cavity, where the patterned portion of the substrate within one or more gate regions is encapsulated by the insulting layer and the liner.

Abstract: InGaN/GaN quantum layer nanowire light emitting diodes are fabricated into a single cluster capable of exhibiting a wide spectral output range. The nanowires having InGaN/GaN quantum layers formed of quantum dots are tuned to different output wavelengths using different nanowire diameters, for example, to achieve a full spectral output range covering the entire visible spectrum for display applications. The entire cluster is formed using a monolithically integrated fabrication technique that employs a single-step selective area epitaxy growth.

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Abstract: Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a second conductor and a plurality of air gaps. The two gate structures are located on a surface of a semiconductor material substrate. The first conductor is disposed between the two gates structures. The barrier is disposed between the first conductor and the gate structure. The second conductor is disposed on the first conductor. The air gaps are disposed at two sides of the second conductor. A width of the second conductor is greater than a width of the first conductor.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes an NMOS device formed on a first substrate bonded with a second substrate having a PMOS device formed thereon, with the bonding achieved by contacting a first wiring layer formed on the NMOS device with a second wiring layer formed on the PMOS device.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

Abstract: Various transistors, such as horizontal gate-all-around transistors, and methods of fabricating such are disclosed herein. An exemplary transistor includes a first nanowire and a second nanowire that include a first semiconductor material, a gate that wraps a channel region of the first nanowire and the second nanowire, and source/drain feature that wraps source/drain regions of the first nanowire and the second nanowire. The source/drain feature includes a second semiconductor material that is configured differently than the first semiconductor material. In some implementations, the transistor further includes a fin-like semiconductor layer disposed over a substrate. The first nanowire and the second nanowire are disposed over the fin-like semiconductor layer, such that the first nanowire, the second nanowire, and the fin-like semiconductor layer extend substantially parallel to one another along the same length-wise direction.