Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

Abstract: Methods of manufacturing a wavelength-converting pixel array structure, methods of manufacturing a light-emitting device and light-emitting devices are described. A method of manufacturing a wavelength-converting pixel array structure includes forming, in a recess in a wafer, an array of photoresist blocks separated by gaps. A liquid precursor filler material is dispensed into the recess to fill the gaps with the liquid precursor filler material to form a grid. The photoresist blocks are removed to expose an array of cavities defined by walls in the grid. Each of the cavities is filled with a wavelength-converting material to form wavelength-converting pixels of the wavelength-converting pixel array structure.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

Abstract: A display device includes a display layer having a plurality of organic light-emitting diodes (OLEDs) and an encapsulation layer covering a light-emitting side of the display layer. The encapsulation layer includes a plurality of first polymer projections on display layer, the plurality of first polymer projections having spaces therebetween, and a first dielectric layer conformally covering the plurality of first polymer projections and any exposed underlying surface in the spaces between the first polymer projections, the dielectric layer forming side walls along sides of the first polymer projections and defining wells in spaces between the side walls.

Abstract: Techniques, materials, and structures for stretchable semiconductor nanomesh structures are described. In one embodiment, a stretchable semiconductor nanomesh structure may include a nanomesh formation of certain semiconductor material comprising a network of traces forming at least one opening between sidewalls of the nanomesh formation material, and a substrate configured to support the nanomesh formation material. Other embodiments are described.

Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of first and second silicon germanium layers, and a plurality of silicon layers in a stacked configuration. The stacked configuration includes a repeating arrangement of a silicon layer stacked on an arrangement of at least one of the first and at least two of the second silicon germanium layers. The first and second silicon germanium layers are etched from exposed lateral sides, and plurality of first inner spacers are formed adjacent remaining portions of the first and second silicon germanium layers. Parts of the remaining portions of the second germanium layers are positioned between the first inner spacers and the silicon layers. The method also includes forming a plurality of second inner spacers, and removing the remaining portions of the first and second silicon germanium layers, leaving spaces between the first inner spacers and the silicon layers.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: A method of fabricating at least one single-crystal alloy semiconductor structure. At least one seed, containing an alloying material, on a substrate for growth of at least one single-crystal alloy semiconductor structure is formed. At least one structural form, formed of a host material, on the substrate is crystallized to form the at least one single-crystal alloy semiconductor structure. The at least one structural form is heated such that the material of the at least one structural form has a liquid state. Also, the at least one structural form is cooled, such that the material of the at least one structural form nucleates at the least one seed and crystallizes as a single crystal to provide at least one single-crystal alloy semiconductor structure, with a growth front of the single crystal propagating in a main body of the respective structural form away from the respective seed.

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers that are alternately stacked with each other, a first channel layer passing through the stack structure and including a metal oxide-based semiconductor, and a second channel layer adjacent to the first channel layer and including the metal oxide-based semiconductor, wherein the first channel layer has a higher oxygen content than the second channel layer and has a different thickness from the second channel layer.

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.