Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: A MOSFET and IGBT are described that exhibit high breakdown voltage together with low on-resistance. This is achieved by providing an N type shunt that extends from the N+ drain (for power MOSFETs) or P+ emitter (for IGBTs), through the N− region to a short distance below the gate oxide. To manufacture such a shunt, an epi wafer with N−epitaxy is first provided on top of an N+ (for power MOSFET) or P+ (for IGBT) layer. Through a suitable mask (contact or freestanding) on the top surface, the wafer is then subjected to bombardment by protons or deuterons. Because of ion transmutation doping, a region of N type material forms wherever the surface is not masked. By controlling the energies of the ions, this region is caused to extend below the wafer's surface so as to just contact the N+ or P+ layer or even to go through it.

Abstract: A micromachined accelerometer is hermetically sealed in a reduced oxygen environment to allow organics to survive high temperature sealing processes.

Abstract: Circuitry 400 for controlling a bidirectional terminal includes an output transistor 405 for selectively coupling the bidirectional terminal to a voltage rail, output transistor 405 turning on when a voltage at a control node falls below a preselected threshold voltage. A diode 402 is coupled to the control node and has a threshold voltage lower than the threshold voltage of the transistor for maintaining the output transistor in a substantially turned off state by maintaining the voltage at the control node above the VDD−VT, where VDD is the supply voltage and VT is the threshold voltage of transistor 405.

Abstract: A magnetic memory cell is disclosed having a structure that prevents disruptions to the magnetization in the sense layer of the magnetic memory cell. In one embodiment, the structure includes a high permeability magnetic film that serves as a keeper for the sense layer magnetization. The keeper structure provides a flux closure path that directs demagnetization fields away from the sense layer. In another embodiment, the structure contains a hard ferromagnetic film that applies a local magnetic field to the sense layer in the magnetic memory cell.

Abstract: A method of forming a non-volatile memory cell having a floating gate with sharp corners is disclosed. First, a first dielectric layer and a first silicon layer are formed on a semiconductor substrate. An etching stop layer is next formed on the first silicon layer. After patterning the etching stop layer to form an opening, a dish-shaped hole is formed by performing an isotropic etching process to partially etch the first silicon layer through the opening. After removing the etching stop layer, a second dielectric layer is formed to refill the dish-shaped hole. After that, a dielectric stud is formed by performing a planarization process to remove a portion of the second dielectric layer outside the dish-shaped hole. Thereafter, a floating gate with sharp corners is formed by performing an anisotropical etching process to etch an exposed portion of the first silicon layer using the dielectric stud as an etching mask. Finally, the dielectric stud is removed.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

Abstract: A method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semi conductor device thereby formed. The method reduces the drift velocity which then decreases the Cu migration rate in addition to void formation rate.

Abstract: Methods of forming mask patterns and methods of forming field emitter tip masks are described. In one embodiment a first surface is provided over which a mask pattern is to be formed. A mixture comprising mask particles is applied to a second surface comprising material joined with the first layer. The mixture, as applied, leaves an undesirable distribution of mask particles over the first surface. After application of the mixture to the second surface, the mask particles are laterally distributed over the first surface, into a desirable distribution by placing a particle-dispersing structure directly into the mixture on the second surface and moving the particle-dispersing structure laterally through the mixture on the second surface. In another embodiment, a mixture is formed on the substrate's second surface and includes a liquid component and a plurality of solid mask-forming components.

Abstract: Methods of forming capacitors and related integrated circuitry are described. In a preferred embodiment, the capacitors form part of a dynamic random access memory (DRAM) cell. According to one aspect of the invention, a first insulating layer is formed over a semiconductive material layer. A conductive gate is formed over the semiconductive material layer. A second insulating layer is formed over the gate and thereafter etched to form a capacitor container. In one implementation, such etch is conducted to outwardly expose the semiconductive material layer. In another implementation, such etch continues into the semiconductive material layer. In yet another implementation, such etch is conducted completely through the semiconductive material layer and into the first insulating layer. In a preferred implementation, a storage capacitor is formed within the capacitor container which extends both elevationally above and elevationally below the gate.

Abstract: The present invention includes electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive. In one embodiment, an electrical interconnection configured to electrically couple a first substrate and a second substrate includes: a bond pad of the first substrate having a male configuration; and a bond pad of the second substrate having a female configuration, the bond pad of the second substrate being configured to mate with the bond pad of the first substrate during electrical connection of the bond pads of the first substrate and the second substrate. A method of conducting electricity according to the present invention includes providing first and second bond pads individually defining a planar dimension; coupling the first and second bond pads at an interface having a surface area greater than the area of the planar dimension; and conducting electricity between the first and second bond pads following the coupling.

Abstract: To offer a technique that can form electrodes in a composite device without using a lift-off method. In the manufacture of a composite device 2 in which a wafer 50 that has a sacrificial layer 51 is used, a mask film 66 that has been patterned is formed; patterning is given to a structural layer 54, the sacrificial layer 51 is etched from the area that is exposed, a movable part 11 is formed in an area where said sacrificial layer 51 is removed, and a fixed part 10 is formed in an area where the sacrificial layer 51 remains; also, a thin metallic film 60 is formed and patterning is given before forming the mask film 66, with electrodes 37 for an external electrical connection being formed. A protective film thin titanium tungsten film 64 is formed on the surface of said thin metallic film 60, with the thin metallic film 60 being protected during etching of the sacrificial layer 51.

Abstract: When forming electrodes for an optical waveguide element, a metal film is formed on a surface of a substrate, and openings of predetermined shapes are formed in the metal film. Then proton exchange is carried out on the surface of the substrate with the metal film used as a mask, and optical channel waveguides are thus formed. At least a part of edge portions of the metal film defining the openings is left on the substrate and the metal film is plated with plating metal. The metal film plated with the plating metal is processed into electrodes of predetermined shapes for applying an electric voltage to the optical channel waveguides.

Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.

Abstract: A method of forming an isolation trench structure wherein the dielectric material filling the trench extends beyond the trench edges thereby preventing gaps at the trench edges. A layer of first dielectric is formed on a silicon substrate and a layer of silicon, either polysilicon or amorphous silicon, or silicon nitride is formed on the layer of first dielectric. A resist mask having a trench opening is then formed on the layer of silicon or silicon nitride. An isotropic lateral etch, either a plasma isotropic lateral etch or a chemical wet etch, is then used to etch that part of said silicon or silicon nitride directly under the trench opening in the resist mask and to undercut the silicon or silicon nitride a first distance beyond the edge of the trench opening in the resist mask, thereby forming an oversize trench opening in the layer of silicon or silicon nitride. The trench opening is then transferred to the layer of first dielectric and a trench is formed in the silicon substrate.

Abstract: A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.

Abstract: A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).

Abstract: An electrode for a capacitor having two electrodes and a capacitor insulation layer formed of a dielectric film sandwiched between the two electrodes, at least one of the electrodes being formed of a metal layer and a metal oxide layer, and the metal oxide layer being formed by oxidizing a surface of the metal layer on the basis of a diffusion-controlling reaction and being positioned in an interface to the capacitor insulation layer.

Abstract: A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.