Abstract: A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer is formed on the substrate structure. Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer is formed over the silicon oxynitride layer and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm 250 nm, the silicon oxynitride layer provides a phase-cancel effect.

Abstract: A workpiece and method are provided for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device. The workpiece includes an active area and N potential contact openings covered with a dielectric layer, a first through hole etched in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, a monolithic polysilicon plug deposited in the first through hole, and N−1 second through holes etched in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2. According to one aspect of the invention, the workpiece includes N−1 conductors traversing the active area, the N contact openings are disposed adjacent to the N−1 conductors, and each of the N contact openings is separated from the other contact openings by one of the N−1 conductors.

Abstract: A method of in-situ formation of ferroelectric films including the steps of: forming a starting layer of metal on top of an oxide layer, wherein the metal for the starting layer is capable of forming a ferroelectric material by reducing the underlying oxide layer. Further incorporating into the starting layer at least a second metal capable of being oxidized by the products of the reduction of the oxide layer by the first metal, forming a layer containing a plurality of metals; and heating the plurality of metals layer in the presence of nitrogen.

Abstract: An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

Abstract: A process for forming a nanoporous silica dielectric coating on a substrate. A substrate containing a deposited film is suspended within a sealable hotplate, while remaining free of contact with the hotplate. The hotplate is sealed and an inert gas is flowed across the substrate. The hotplate is heated to a temperature of from about 350° C. or higher, and the substrate is forced to contact the heated hotplate. The substrate is heated for a time that sufficiently removes outgassing remnants from the resultant nanoporous dielectric coating.

Abstract: There is described a method of making a bonded wafer by diffusing regions of a first wafer proximate a first major surface. Trenches are etched a predetermined distance into the first wafer from the first major surface toward a second major surface. The first major surface and trenches are coated with oxide. The first major surface of the first wafer is bonded to a second wafer to form a bonded wafer. The second major surface of the bonded wafer which is also the second major surface of the first wafer is ablated until oxide in the trenches is detected. The bonded wafer is cut into chips which are packaged as integrated circuits.

Abstract: The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.

Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided.

Abstract: A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments.

Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.

Abstract: Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

Abstract: A method is proposed that functions to produce Zener diodes. The method includes a two-part film diffusion step for producing flatter and deeper doping profiles using neutral films.

Abstract: A method is provided for manufacturing, the method including processing a workpiece in a processing step, measuring a critical dimension of features formed on the workpiece using a test structure formed on the workpiece, the test structure including a plurality of the features, and forming an output signal corresponding to the critical dimension measurements. The method also includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step if the output signal corresponding to the critical dimension measurements indicates a predetermined tolerance value has been exceeded.

Abstract: A method and system for processing an amorphous silicon thin film sample to produce a large grained, grain boundary-controlled silicon thin film. The film sample includes a first edge and a second edge. In particular, using this method and system, an excimer laser is used to provide a pulsed laser beam, and the pulse laser beam is masked to generate patterned beamlets, each of the patterned beamlets having an intensity which is sufficient to melt the film sample. The film sample is continuously scanned at a first constant predetermined speed along a first path between the first edge and the second edge with the patterned beamlets. In addition, the film sample is continuously scanned at a second constant predetermined speed along a second path between the first edge and the second edge with the patterned beamlets.

Abstract: Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer. There is also formed over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer. Within the method: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.

Abstract: A method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity is disclosed. In order to effectively prevent wafers from contaminations, the invention uses an additional silane purge process in situ before performing a SHSG seeding process on the wafers. The silane purge process of this invention utilizes the original silane seeding gas inlet. In this manner, not only thicknesses and surface areas of the SHSG seeds and capacitances of DRAMs can be increased, but also wafer-to-wafer uniformity can be upgraded.

Abstract: A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

Abstract: A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 &mgr;m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.