Abstract: The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna ratio of a semiconductor device, determines an oxide area of the semiconductor device and determines a failure fraction of the semiconductor device as a function of the oxide stress voltage and the oxide area.

Abstract: A capacitor for a semiconductor device is fabricated by a method which reduces the interaction of a capacitor electrode and a dielectric layer in the capacitor. One or more passivation layers are formed at the interface between the dielectric layer and an electrode in the capacitor by exposing the dielectric layer or electrode to a reactive environment during fabrication in order to form a passivation layer thereon prior to forming an overlying dielectric layer or electrode. The passivation layer reduces the diffusion of oxygen from the dielectric layer to the electrode, resulting in reduced current leakage in the capacitor.

Abstract: The present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer, (c) forming a second metal layer over the tungsten silicide nitride layer, and (d) annealing the metal stack structure at a diffusion temperature. The tungsten silicide nitride layer inhibits diffusion of the metal in the metal stack. In one embodiment, the annealing is performed in the presence of a forming gas mixture comprising deuterium. In one particularly advantageous embodiment, the metal stack is formed in a contact opening or via. In yet other embodiments, the first metal layer may be a stack layer of titanium and titanium nitride and the second metal layer may be aluminum or copper.

Abstract: The present invention describes an improved process for forming an aluminum or aluminum alloy plug in the fabrication of a semiconductor device. An opening is formed in a wafer. A titanium wetting layer is then deposited over the wafer and lines the sidewalls and bottom of the opening. A first aluminum deposition step is performed at a first power in a hot deposition chamber. A second aluminum deposition step is performed at a second higher power in a cold deposition chamber. The present invention forms the aluminum plug without the problems of void formation and without reaching temperatures that could cause damage to underlying layers during the fabrication process.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. The trenches are formed using a stop layer so that the depth of the trenches may be precisely controlled. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of dielectric material, and a conductive material. The has a surface and the plurality of adjacent conductive strips is disposed on the substrate surface with each adjacent conductive strip having a length. The layer of dielectric material is deposited over the substrate surface and over and around the plurality of adjacent conductive strips to form at least two opposing, contoured, merging dielectric surfaces, each of which overhangs the substrate surface located between at least two of the plurality of adjacent conductive strips. The at least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening and is substantially encased therein and which extends along the length.

Abstract: Semiconductor packages which are prepared by forming circuit substrates, mounting IC chips on the circuit substrates, encapsulating the IC chips on the circuit substrates with resin, and forming electrodes, are attached to a standard member. After this attaching step, the semiconductor packages are subjected to a cutting step where the semiconductor packages are diced into a plurality of circuit substrates.

Abstract: The present invention provides a method of manufacturing VCSELs which involves a flip-bonding process wherein the top surface of the VCSEL wafer is bonded face down onto a surrogate substrate. The process begins in a manner similar to traditional double dielectric stack based VCSEL, but then involves flip-bonding the wafer onto an In or Ag epoxy coated surrogate substrate. The InP substrate is then selectively etched. After flip-bonding the wafer fabrication proceeds on the freshly etched surface which now forms the top surface. Next, standard mesa-isolation and contact formation techniques are performed on this newly etched surface.

Abstract: The data of a plurality of attributes of dies on a semiconductor wafer under a parametric test can be managed in a unified manner, and edited and displayed on a real-time basis with one tool. A semiconductor inspection apparatus has a memory for expanding and storing attribute data of dies as data of at least three values for selecting and specifying attributes of dies on a wafer from a plurality of attributes, and a display controller for allowing an operator to select any of the attributes of dies within one displayed image, and reflecting selected attributes immediately as die characteristics in the displayed image. A method of specifying attributes of dies on a wafer in such a semiconductor inspection apparatus is also disclosed.

Abstract: A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer.

Abstract: A method of forming a desired rectangular pattern in a material layer above a substrate. The method includes providing a substrate having a material layer thereon. A hard mask layer is next formed over the material layer, and then a first photoresist layer having a first pattern therein is formed over the hard mask layer. A first etching operation is carried out while using the first photoresist layer as an etching mask to remove a portion of the hard mask layer, thereby transferring the pattern in the first photoresist layer to the hard mask layer. The first photoresist layer is removed. A second photoresist layer having a second pattern therein is formed over the substrate. A second etching operation is carried out to remove a portion of the material layer while using the patterned second photoresist layer and the hard mask layer as an etching mask. Hence, the desired rectangular pattern is formed in the material layer.

Abstract: There is disclosed a method of fabricating an SOI wafer by a hydrogen ion delamination method wherein a surface of an SOI layer is not polished but is subjected to heat treatment in a reducing atmosphere containing hydrogen after a bonding heat treatment, a method of fabricating an SOI wafer by a hydrogen ion delamination method wherein a surface of an SOI layer is not polished but subjected to heat treatment in a reducing atmosphere containing hydrogen after delaminating heat treatment, and a SOI wafer fabricated by the methods. There are provided a method of fabricating an SOI wafer by a hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination is removed and surface roughness is improved without polishing, so that uniform thickness of the SOI layer can be achieved, and to simplify the process therefor.

Abstract: A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: An amorphous silicon thin film transistor for active matrix liquid crystal displays according to the present invention comprises a transparent conductive film, which is formed together with a picture element electrode, a metal film, which is formed together with a signal wiring, a multi-layer film, and an insulation substrate. The multi-layer film, which consists of a semi-conductor film, a gate insulation film and a gate metal film, is placed on the transparent conductive film and metal film overlapping respectively at both edges of the multi-layer film.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; forming nickel silicide layers disposed on the source/drain regions and the gate electrode, and two etching steps. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The first etch is performed with a sulfuric peroxide mix to remove unreacted nickel, and the second etch is performed with an ammonia peroxide mix to remove nickel silicide formed over the first and second sidewall spacers.

Abstract: A method for forming flip chip bumps or UBM for a high speed copper interconnect chip, and more particularly to a method for forming a flip chip bump or UBM of copper/nickel, copper/nickel/copper or etc. which are carried out by a subsequent process of electroless copper plating and electroless nickel plating on a copper I/O pad. According to the method, both of electroless copper and nickel plating methods are used for forming electroless copper/nickel bumps of a copper interconnect chip so that advantages of the electroless copper plating, i.e. excellent selectivity and adhering strength to the copper chip pad and an advantage of the electroless nickel plating, i.e. excellent plating rate can be achieved at the same time.

Abstract: A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

Abstract: A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second via

Abstract: A substrate (901 in FIGS. 1A and 1B) is overlaid with a base film (902), an amorphous semiconductor film (903) and a first protective insulating film (904), and a thermal conduction layer (905) having a light transmissivity is selectively formed. Subsequently, the amorphous semiconductor film (903) is crystallized by laser annealing. The thermal conduction layer (905) functions to control the outflow rate of heat from the semiconductor film (903), and a crystalline semiconductor film centering round a region formed with the thermal conduction layer (905) is prepared by utilizing the difference of temperature distributions over the substrate (901). In the crystalline semiconductor film thus prepared, the location and size of a crystal grain have been controlled. A TFT capable of high-speed operation is realized by employing the crystalline semiconductor film as the channel forming region of the TFT.