Abstract: A protective film forming method is provided. In the method, substantially an entire surface of a silicon-containing underfilm is terminated with fluorine by supplying a fluorine-containing gas to the silicon-containing underfilm formed on a substrate having a surface including a plurality of recesses and a flat surface provided between the adjacent recesses. A surface of the silicon-containing underfilm formed on the flat surface of the substrate is nitrided by supplying a nitriding gas converted to plasma to the silicon-containing underfilm terminated with fluorine such that a silicon adsorption site is formed on the surface of the silicon-containing underfilm formed on the flat surface of the substrate. A silicon-containing gas is adsorbed on the silicon adsorption site by supplying the silicon-containing gas to the silicon-containing underfilm.

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

Abstract: The present disclosure relates to a semiconductor device, an array substrate, and a method for fabricating the semiconductor device. The semiconductor device comprises a substrate, a thin film transistor formed on the substrate, and a first light detection structure adjacent to the thin film transistor, wherein the first light detection structure includes a first bottom electrode, a top electrode, and a first photo-sensing portion disposed between the first bottom electrode and the first top electrode, one of a source electrode and a drain electrode of the thin film transistor is disposed in the same layer as the first bottom electrode of the first light detection structure; the other of the source electrode and the drain electrode of the thin film transistor is used as the first top electrode.

Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

Abstract: A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: Methods of generating structural models of highly deviated or horizontal wells may be generated from the measurement of true stratigraphic thickness in three dimensions (TST3D). In one aspect, methods may include generating a structural model from one or more deviation surveys of a horizontal well, one or more single channel log measurements, and a three-dimensional reference surface.

Abstract: A photovoltaic device includes an intrinsic layer having two or more sublayers. The sublayers are intentionally deposited to include complementary concave and convex shapes. The sum of these layers resulting in a relatively flat surface for deposition of n- or p-doped layers. The photovoltaic device is optionally bifacial.

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Abstract: There is provided improved accuracy in cargo handling by a spreader (306) including a distance sensor (308a, 308b) transmitting optical signals. The handled cargo (312) includes a plurality of interconnected sides (312a, 312b). The transmission directions of the optical signals are selected and distances are measured by reflected optical signals transmitted in the selected directions. The measured distances are used to determine a reference line that matches a shape of at least one of the interconnected sides (312a, 312b) of the cargo (312).

Abstract: An organ light-emitting diode (OLED) display panel manufacturing method and an OLED display panel manufacturing device, the device includes a chamber configured to accommodate and heating an OLED lamination plate, where he OLED lamination plate has a substrate and a packaging lid adhered by glass adhesive and UV adhesive; a transparent lamination plate located in the chamber and configured to laminate the OLED lamination plate; a laser head located in the chamber, located on a side of the packaging lid above the transparent lamination plate and utilizing the laser beam irradiate a protruding portion of a start point of the glass adhesive.

Abstract: High-power remote phosphor white LED heat-dissipation package relates to an LED heat-dissipation package, for solving the problem of poor heat dissipation of LED package structures. The substrate of the package structure is provided with a boss and a heat conducting ring, and the phosphor structural layer contains hollow glass microspheres. The white LED heat-dissipation package structure in the present invention improves the spatial chroma uniformity of the white light by using the hollow glass microspheres, thereby reducing the costs. The package structure can improve the heat dissipation efficiency of the chip and the utilization ratio of light emitted from the chip. The present invention is applicable to prepare high-power remote phosphor white LEDs.

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.

Abstract: The present disclosure relates to a display substrate comprising a substrate; a data line disposed over the substrate; a first insulating layer disposed on the data line; a second insulating layer disposed on the first insulating layer; a first transparent electrode disposed on the second insulating layer. The present disclosure further relates to a manufacturing method of a display substrate and a display device.

Abstract: A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.

Abstract: A pressure deviation between a setpoint tire pressure and an actual tire pressure for a tire of a vehicle is determined by the following steps: Ascertaining a wheel load for the tire. Ascertaining a dynamic tire radius of the tire. Determining the pressure deviation as a function of the wheel load and the dynamic tire radius.

Abstract: According to the invention a method for filling one or more gaps created during manufacturing of a feature on a substrate is provided by providing the substrate in a reaction chamber and providing a deposition method. The deposition method comprises; providing an anisotropic plasma to bombard a bottom area of a surface of the one or more gaps with ions thereby creating adsorption sites at the bottom area; introducing a first reactant to the substrate; and, allowing the first reactant to react with the adsorption sites at the bottom area of the surface to fill the one or more gaps from the bottom area upwards.

Abstract: A lead frame includes a frame part, a lead extending inward from the frame part and having a front surface and a back surface, and an external connection terminal formed at a part of the lead in an extension direction and protruding from the back surface of the lead. The lead includes a pentagonal shape in a cross-section where the front surface of the lead faces upward, the pentagonal shape having a quadrangular main body part and a triangular protrusion protruding from a lower surface of the main body part. A width of a lower end of the main body part is smaller than a width of an upper end of the main body part.