Abstract: A wiring board includes an insulating layer, a plurality of pads formed on a surface of the insulating layer, and a chip mounting region defined on a surface of the wiring board formed with the plurality of pads. The plurality of pads are arranged in the chip mounting region. A cavity is formed in a surface of at least some of the plurality of pads. The cavity caves in, from the surface of the at least some of the plurality of pads, toward the insulating layer. The chip mounting region is segmented into a plurality of segmented regions, and a depth of the cavity is different for each of the plurality of segmented regions.

Abstract: Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: A method of fabricating a semiconductor device includes forming a back gate dielectric. A layer of two-dimensional material is transferred onto a surface of the back gate dielectric. A top gate dielectric is deposited and a top gate formed thereon. A first set of spacers is formed around the top gate and exposed portions of the top gate dielectric removed and a second set of spacers formed around the top gate. Exposed portions of the two-dimensional material are removed. A directional etch down of the substrate and a lateral isotropic etch of the substrate are performed and open spaces filled with a dielectric material surrounding the top gate, the back gate dielectric, and the substrate. The dielectric material is etched from the top gate and the back gate dielectric, the second set of spacers removed, and source and drain contact metal deposited. The source and drain contacts the layer.

Abstract: The present disclosure provides a method for characterizing ohmic contact electrode performance of a semiconductor device. The method comprises: preparing two sets of testing patterns on a semiconductor device; testing resistance values of the two sets of testing patterns respectively; calculating a sheet resistance of an ohmic contact area according to the obtained resistance values; and evaluating the ohmic contact electrode performance of the semiconductor device according to the sheet resistance of the ohmic contact electrode.

Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.

Abstract: An optical waveguide substrate 1 includes an optical waveguide 9 composed of a multi-layered film 4 of a plurality of optical material films 5, 6 and having end faces onto which a light is made incident or from which the light is emitted. The end face is an etched surface, and it is provided, on the end face, an unevenness 7 corresponding to a difference of etching rates of the optical material films.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract: The present disclosure provides a method for manufacturing an LTPS thin film transistor which includes: forming a light shielding pattern and an active layer of the LTPS thin film transistor on a base substrate through one single patterning process, in which an orthogonal projection of the active layer on the base substrate falls within an orthogonal projection of the light shielding pattern on the base substrate, and the light shielding pattern is made of a semiconductor material.

Abstract: A solid state imaging device has a global shutter structure and includes: a photodetector; a wiring layer; a first transparent insulating film disposed immediately above the photodetector and penetrating the wiring layer; a transparent protective film covering the wiring layer and the first transparent insulating film, and having a higher refractive index than the first transparent insulating film; a first projection provided on the transparent protective film and having a quadrilateral shape in top view; and a second transparent insulating film having a lower refractive index than the first projection.

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

Abstract: A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive.

Abstract: A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

Abstract: An integrated circuit includes a fluxgate magnetometer. The magnetic core of the fluxgate magnetometer is encapsulated with a layer of encapsulant of a nonmagnetic metal or a nonmagnetic alloy. The layer of encapsulate provides stress relaxation between the magnetic core material and the surrounding dielectric. A method for forming an integrated circuit has the magnetic core of a fluxgate magnetometer encapsulated with a layer of a nonmagnetic metal or nonmagnetic alloy to eliminate delamination and to substantially reduce cracking of the dielectric that surrounds the magnetic core.

Abstract: A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.

Abstract: A semiconductor structure is provided that includes a fin stack structure of, from bottom to top, a first semiconductor material fin portion, an insulator fin portion and a second semiconductor material fin portion. The first semiconductor material fin portion can be used as a first device region in which a first conductivity-type device (e.g., n-FET or p-FET) can be formed, while the second semiconductor material fin portion can be used as a second device region in which a second conductivity-type device (e.g., n-FET or p-FET), which is opposite the first conductivity-type device, can be formed.

Abstract: A substrate for a power module (100) of the present invention includes a metal substrate (101), an insulating resin layer (102) provided on the metal substrate (101), and a metal layer (103) provided on the insulating resin layer (102). The insulating resin layer (102) includes a thermosetting resin (A) and inorganic fillers (B) dispersed in the thermosetting resin (A), a maximum value of a dielectric loss ratio of the insulating resin layer (102) at a frequency of 1 kHz and 100° C. to 175° C. is equal to or less than 0.030, and a change in a relative permittivity is equal to or less than 0.10.

Abstract: An image sensor is provided. The image sensor includes a visible light receiving portion and an infrared receiving portion. The visible light receiving portion is configured to receive a visible light. The infrared receiving portion is configured to receive infrared. The visible light receiving portion includes an infrared cutoff filter ball layer configured to collect the visible light. In some embodiments of the present invention, the infrared receiving portion includes a micro-lens layer configured to collect the infrared. In some other embodiments of the present invention, the infrared receiving portion includes an infrared pass filter ball layer configured to collect the infrared.

Abstract: There is provided a self-supporting polycrystalline gallium nitride substrate having excellent characteristics such as high luminous efficiency and high conversion efficiency when used for devices, such as light emitting devices and solar cells. The self-supporting polycrystalline gallium nitride substrate is composed of gallium nitride-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate, and has a top surface and a bottom surface. The crystal orientations of individual gallium nitride-based single crystal grains as determined from inverse pole figure mapping by electron backscatter diffraction (EBSD) analysis on the top surface are distributed at various tilt angles from the specific crystal orientation, in which the average tilt angle thereof is 0.1° or more and less than 1° and the cross-sectional average diameter DT of the gallium nitride-based single crystal grains at the outermost surface exposed on the top surface is 10 ?m or more.