Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1<a2. The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.

Abstract: An apparatus for positioning micro-devices on a substrate includes one or more supports to hold a donor substrate and a destination substrate, an adhesive dispenser to deliver adhesive on micro-devices on the donor substrate, a transfer device including a transfer surface to transfer the micro-devices from the donor substrate to the destination substrate, and a controller. The controller is configured to operate the adhesive dispenser to selectively dispense the adhesive onto selected micro-devices on the donor substrate based on a desired spacing of the selected micro-devices on the destination substrate. The controller is configured to operate the transfer device such that the transfer surface engages the adhesive on the donor substrate to cause the selected micro-devices to adhere to the transfer surface and the transfer surface then transfers the selected micro-devices from the donor substrate to the destination substrate.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: An electronic device includes an electronic component, a sealing resin body, and a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to the outside of the sealing resin body, and having different potentials. The conductive members include a heat sink and a terminal extending from an inside to the outside of the sealing resin body. A surface of the terminal includes, as a part covered with the sealing resin body, a higher adhesion part and a lower adhesion part. The lower adhesion part is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component. The higher adhesion part is provided in the connection surface.

Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.

Abstract: A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed.

Abstract: A display device may include a substrate, an active pattern layer, a gate insulating layer, a first metal pattern layer, an interlayer insulating layer, a second metal pattern layer, and a passivation film. The active pattern layer may be disposed on the substrate. The gate insulating layer may be disposed on the active pattern layer. The first metal pattern layer may be disposed on the gate insulating layer. The interlayer insulating layer may be disposed on the first metal pattern layer. The second metal pattern layer may be disposed on the interlayer insulating layer. The passivation film may be disposed on the side wall of the second metal pattern layer.

Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

Abstract: The invention teaches a system and method for reducing energy consumption in commercial buildings. The invention provides development of certain mechanical heat profiles and use of such profiles in an automated optimization method. Outputs communicate with the building management system of the commercial building, and regulate the heating system during a season when the building activates the heating system. Various embodiments are taught.

Abstract: An integrated circuit includes a fluxgate magnetometer. The magnetic core of the fluxgate magnetometer is encapsulated with a layer of encapsulant of a nonmagnetic metal or a nonmagnetic alloy. The layer of encapsulate provides stress relaxation between the magnetic core material and the surrounding dielectric. A method for forming an integrated circuit has the magnetic core of a fluxgate magnetometer encapsulated with a layer of a nonmagnetic metal or nonmagnetic alloy to eliminate delamination and to substantially reduce cracking of the dielectric that surrounds the magnetic core.

Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.

Abstract: In manufacturing a crystalline silicon-based solar cell having an intrinsic silicon-based thin film and a conductive silicon-based thin film in this order on a conductive single-crystalline silicon substrate, plasma treatment is performed after the intrinsic silicon-based thin film is formed on the conductive single-crystalline silicon substrate. In the plasma treatment, a surface of the intrinsic silicon-based thin film is exposed to hydrogen plasma while a hydrogen gas and silicon-containing gases are being introduced into a CVD chamber. The amount of the hydrogen introduced into the CVD chamber during the plasma treatment is 150 to 2500 times the introduction amount of the silicon-containing gases.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact.

Abstract: Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Abstract: A method for manufacturing a semiconductor structure, including: direct bonding a substrate to be handled with a handle substrate via a bonding layer covering the handle substrate, to form a temporary structure capable of withstanding technological steps; disassembling the temporary structure at the bonding layer to separate the substrate to be handled from the handle substrate; and a prior depositing the bonding layer onto the handle substrate and/or onto the substrate to be handled, the bonding layer including a porous material including, an inorganic matrix and organic compounds connected or not to the matrix, and the disassembling is carried out by providing a thermal budget for disassembly to the intermediate structure, the providing resulting in a spontaneous disassembly of the temporary structure occurring at the bonding layer.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one FinFET device. The FinFET device includes a substrate, a plurality of fins protruding from the substrate, at least one gate structure on the substrate and across the plurality of fins by covering portions of side and top surfaces of the plurality of fins, and source/drain regions formed in the plurality of fins at two sides of the gate structure. The semiconductor device also includes a Fuse device formed above the FinFET device. The Fuse device includes a positive terminal and a negative terminal. The negative terminal is electrically connected to at least one source region of the FinFET device and the positive terminal is electrically connected to an external pad. Further, the semiconductor device also includes a dielectric layer formed between the FinFET device and the Fuse device.

Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.

Abstract: An image-capturing element manufacturing method includes: preparing a first substrate having a plurality of pixels that are two-dimensionally continuously arrayed; preparing a second substrate having a plurality of circuit blocks that respectively have connection terminals to a power supply and a reference potential and that are electrically independent from each other, each of the plurality of circuit blocks having at least some of circuits to read out signals from the plurality of pixels; laminating the first substrate and the second substrate to electrically couple the plurality of circuit blocks and the plurality of pixels overlapping therewith; and cutting circuit blocks around at least one of the plurality of circuit blocks and pixels overlapping therewith to form a laminate in which the plurality of pixels are laminated onto the at least one of the plurality of circuit blocks.