Patents Examined by Charles Garber
  • Patent number: 9862595
    Abstract: A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam patt
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 9, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Errong Jing
  • Patent number: 9857688
    Abstract: A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9850132
    Abstract: Provided is a method for growing carbon nanotubes that enables the growth of high-density carbon nanotubes. A high frequency bias voltage is applied to a loading table on which a wafer W having a catalytic metal layer is mounted to generate a bias potential on the surface of the wafer W, and oxygen plasma is used to micronize the catalytic metal layer to form catalytic metal particles. Thereafter, hydrogen plasma is used to reduce the surface of the catalytic metal particles to form activated catalytic metal particles having an activated surface. By using each activated catalytic metal particles as a nucleus, carbon nanotubes are formed.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 26, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Matsumoto, Kenjiro Koizumi
  • Patent number: 9853192
    Abstract: An apparatus and method for manufacturing a thin film encapsulation includes: a first cluster configured to form a first inorganic layer on a display substrate using a sputtering process; a second cluster configured to form a first organic layer on the first inorganic layer on the display substrate using a monomer deposition process; and a third cluster configured to form a second inorganic layer on the first organic layer on the display substrate using a chemical vapor deposition (CVD) process or a plasma enhanced chemical vapor deposition (PECVD) process.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: December 26, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung-Soo Huh, Jeong-Ho Yi, Yong-Suk Lee
  • Patent number: 9853069
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 9842765
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 9837275
    Abstract: This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N? substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 5, 2017
    Assignee: SHANGHAI IC R&D CENTER CO., LTD
    Inventors: Quan Wang, Jieqiong Dong, Deming Sun, Wei Zhou
  • Patent number: 9835899
    Abstract: A display device includes a first base substrate, a second base substrate, pixels, a first polarizer, and a second polarizer. The first base substrate includes light transmitting areas and a light blocking area surrounding each of the light transmitting areas. The pixels respectively overlap the light transmitting areas. The first and second polarizers are spaced apart from each other such that the pixels are disposed therebetween. At least one of the first and second polarizers includes a plurality of optical conversion layers, each of which comprises a plurality of lattice wires.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae-Young Lee, Donggun Park, Hyang-Shik Kong, Jung Gun Nam, Gugrae Jo
  • Patent number: 9837262
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 5, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Ryota Sasajima, Yoshinobu Nakamura
  • Patent number: 9831083
    Abstract: A film containing a prescribed element and carbon is formed on a substrate, by performing a cycle a prescribed number of times, the cycle including: supplying an organic-based source containing a prescribed element and a pseudo catalyst including at least one selected from the group including a halogen compound and a boron compound, into a process chamber in which the substrate is housed, and confining the organic-based source and the pseudo catalyst in the process chamber; maintaining a state in which the organic-based source and the pseudo catalyst are confined in the process chamber; and exhausting an inside of the process chamber.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 28, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Daigo Yamaguchi, Tsukasa Kamakura, Hiroshi Ashihara, Tsuyoshi Takeda, Taketoshi Sato
  • Patent number: 9829415
    Abstract: In a metrology sampling method, various index values that can detect various status changes of a process tool (such as maintenance operation, parts changing, parameter adjustment, etc.), and/or information abnormalities of the process tool (such as abnormal process data, parameter drift/shift, abnormal metrology data, etc.) appear in a manufacturing process are applied to develop an intelligent sampling decision (ISD) scheme for reducing sampling rate while VM accuracy is still sustained. The indices includes a reliance Index (RI), a global similarity index (GSI), a process data quality index (DQIX) and a metrology data quality index (DQIy).
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: November 28, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Fan-Tien Cheng, Chun-Fang Chen, Hsuan-Heng Huang, Chu-Chieh Wu
  • Patent number: 9824982
    Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9812409
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 9812412
    Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 7, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Takuma Shimoichi, Yasuhiro Kondo
  • Patent number: 9806041
    Abstract: According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 31, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck
  • Patent number: 9793121
    Abstract: A method of manufacturing a silicon carbide semiconductor device, having a silicon carbide semiconductor element substrate and a surface electrode film forming an ohmic contact between them. A first electrode film including nickel is formed on the substrate surface. A second electrode film with nickel silicide is formed on a first electrode film surface. The surface film is formed having the ohmic contact between the substrate surface and the first electrode film by annealing to cause silicon of the substrate and nickel of the first electrode film to react and convert the first electrode film to silicide. The first electrode film is formed with a thickness so that during annealing, an amount of carbon atoms is liberated from the substrate and diffuses toward the first electrode film, wherein the liberated amount is equal to or less than the amount of carbon atoms that the second electrode film is able to take in during annealing.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 17, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Patent number: 9786764
    Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Jin Park, Chung-Hwan Shin, Sung-Woo Kang, Young-Mook Oh, Sun-Jung Lee, Jeong-Nam Han
  • Patent number: 9780137
    Abstract: Embodiments of mechanisms for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region formed in the substrate. The radiation-sensing region is operable to detect incident radiation that enters the substrate through the back surface. The radiation-sensing region further includes an epitaxial isolation feature formed in the substrate and adjacent to the radiation-sensing region. The radiation-sensing region and the epitaxial isolation feature have different doping polarities.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 9780031
    Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
  • Patent number: 9780114
    Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 3, 2017
    Assignee: SK Hynix Inc.
    Inventor: Young Jin Lee