Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate. The vertical FET comprises a lower source/drain region disposed on the substrate. The lower source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface, wherein the bottom surface of the lower source/drain region contacts the substrate. A lower metallic contact is disposed adjacent to, and in contact with, at least one sidewall surface of the lower source/drain region, wherein the lower metallic contact comprises a laterally extended portion which laterally extends from the at least one sidewall surface of the lower source/drain region.

Abstract: An emission efficiency of a light-emitting device is improved by reducing strains applied to a light-emitting layer. On a sapphire substrate, an n-type contact layer, an nESD layer, an n-type cladding layer, a light-emitting layer, a p-type cladding layer, and a p-type contact layer, are sequentially deposited. The light-emitting layer has a MQW structure in which a layer unit of a well layer, a capping layer, and a barrier layer sequentially deposited is repeatedly deposited. Of the well layers, the In composition ratio of only first well layer is reduced than the In composition ratios of other well layers, and the In composition ratios of the other well layers are equal to each other. The In composition ratio of the first well layer is designed so that the emission wavelength of the first well layer is equal to the emission wavelengths of other well layers.

Abstract: A semiconductor package may include a first semiconductor die, external connectors, second semiconductor dies, a mold layer, an outer packaging part, and a terrace-like edge. The external connectors may be disposed over a first surface of the first semiconductor die. The second semiconductor dies may be stacked over a second surface of the first semiconductor die. The mold layer may cover sidewalls of the second semiconductor dies. The outer packaging part may have a groove in which a stack structure of the first and second semiconductor dies are accommodated. The terrace-like edge may be disposed under an edge of the mold layer to expose a sidewall of the first semiconductor die. A portion of an outer sidewall of the mold layer may be in contact with a portion of an inner surface of the outer packaging part, and the inner surface of the outer packaging part may be spaced apart from the sidewall of the first semiconductor die by the terrace-like edge.

Abstract: In a method for fabricating a fine structure, a metal oxide layer is formed by using an atomic layer deposition over a substrate, and the metal oxide layer is removed. An interfacial oxide layer is formed between the metal oxide layer and the substrate. The interfacial oxide layer is an oxide of an element constituting the substrate, and the interfacial oxide layer is removed.

Abstract: Embodiments of the invention are directed to a method of separating a wafer of light emitting devices. The light emitting devices are disposed in rows. The method includes dividing the wafer into a plurality of regions. Each region comprises a plurality of rows of light emitting devices and a first region is wider than a second region. For each region, the method includes determining a position of first and second dicing streets. The dicing streets are located between the rows of light emitting devices. The method includes determining, using the position of the first and second dicing streets, positions of a plurality of dicing streets disposed between the first and second dicing streets. The method includes cutting the wafer along streets.

Abstract: A semiconductor device includes a charge-compensating region with a first structure disposed adjoining an end portion of the charge-compensating region. The first structure is configured to reduce charge-imbalances present in the charge-compensating region. In one embodiment, the first structure includes a trench that extends along the vertical depth of the charge-compensated trench so that the final charge-compensating region is provided without corner portions. In one embodiment, a material, such as a dielectric material and/or a polycrystalline semiconductor material, may be disposed within the trench and at least along the end portion of the charge-compensating region. Among other things, the first structure improves device electrical performance and manufacturing yields.

Abstract: Provided are an organic light emitting display (OLED) apparatus and a manufacturing method thereof. The OLED apparatus includes: a thin film transistor (TFT) array substrate including: a support substrate, including a soft material and a plurality of TFTs on the support substrate corresponding to a plurality of pixel areas, a light emitting array (LEA) including a plurality of organic light emitting devices on the TFT array substrate corresponding to the plurality of pixel areas, a sealing structure facing the TFT array substrate, the LEA interposed between the TFT array substrate and the sealing structure, and an adhesive layer between the LEA and the sealing structure to adhere the LEA to the sealing structure, wherein the sealing structure includes: a protective layer on the LEA, a sealing layer over the TFT array substrate, and a barrier layer adhering the protective layer to the sealing layer.

Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) attached to a die paddle segment of a first patterned conduct carrier and coupled to a switch node segment of the first patterned conductive carrier by an electrical connector. In addition, the semiconductor package includes a second patterned conductive carrier situated over the IC, a magnetic material situated over the second patterned conductive carrier, and a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.

Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer which is formed on the semiconductor substrate so as to be in contact with the semiconductor substrate, a first conductivity type body region which is formed in a front surface portion of the semiconductor layer, a second conductivity type source region which is formed in a front surface portion of the body region, a second conductivity type drain region which is formed apart from the body region, a gate insulating film which is formed in a front surface of the semiconductor layer so as to be in contact with the body region, a thick insulating film which is formed integrally with the gate insulating film so as to cover the semiconductor layer between the gate insulating film and the drain region and a gate electrode which is opposite to the body region via the gate insulating film.

Abstract: A semiconductor device includes a substrate provided with active patterns, gate electrodes extending across the active patterns, source/drain regions provided in upper portions of the active patterns between the gate electrodes, respectively, and first contacts and second contacts provided between the gate electrodes and electrically connected to the source/drain regions, respectively. The first and second contacts are disposed in such a way that a contact center line thereof is spaced apart from a corresponding gate center line by first and second distances. The first distance differs from the second distance.

Abstract: A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.

Abstract: A light emitting diode module includes a substrate, a first soldering section, a second soldering section, a block and a light emitting diode die. The substrate has a top surface and includes a circuit structure. The block is formed on the top surface. The soldering section and the second solder section are formed on the top surface of the substrate and electrically connected with the circuit structure. The block is positioned between the first soldering section and the second solder section. A height of the block is larger than thicknesses of the first soldering section and the second soldering section. The light emitting diode die includes a first electrode and a second electrode being respectively electrically connected to the first soldering section and the second soldering section. The block is positioned between the first soldering section and the second soldering section.

Abstract: A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate.

Abstract: After forming a blanket silicon germanium (SiGe) layer over a thinned silicon (Si) layer of a silicon-on-insulator (SOI) substrate, a portion of the SiGe layer located in an n-type FET (nFET) region of the SOI substrate is recessed, while masking another portion of the SiGe layer located in a p-type FET (pFET) region of the SOI substrate. The recessed portion of the SiGe layer in the nFET region is subsequently removed with an in-situ pre-clean etch. An epitaxial Si layer is re-grown in the nFET region over a portion of the thinned Si layer that is exposed by the removal of the recessed portion of the SiGe layer.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

Abstract: According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a semiconductor chip and an activated front surface of a substrate so as to face each other with a back surface of the semiconductor chip attached to a sheet. The bonding method includes pushing the back surface of the semiconductor chip through the sheet to closely attach the activated front surface of the semiconductor chip and the activated front surface of the substrate. The bonding method includes stripping the sheet from the back surface of the semiconductor chip while maintaining a state in which the activated front surface of the semiconductor chip is closely attached to the activated front surface of the substrate.

Abstract: A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP.