Patents Examined by Cheng-Yuan Tseng
  • Scheduling tasks using targeted pipelines
    Patent number: 11366691
    Abstract: A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: June 21, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Simon Nield, Yoong-Chert Foo, Adam de Grasse, Luca Iuliano
  • Chip and chip-based data processing method
    Patent number: 11361217
    Abstract: Embodiments of the present specification provide chips and chip-based data processing methods. In an embodiment, a method comprises: obtaining data associated with one or more neural networks transmitted from a server; for each layer of a neural network of the one or more neural networks, configuring, based on the data, a plurality of operator units based on a type of computation each operator unit performs; and invoking the plurality of operator units to perform computations, based on neurons of a layer of the neural network immediately above, of the data for each neuron to produce a value of the neuron.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: June 14, 2022
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Guozhen Pan, Jianguo Xu, Yongchao Liu, Haitao Zhang, Qiyin Huang, Guanyin Zhu
  • Systems and methods for processing an image
    Patent number: 11354125
    Abstract: A method for processing a medical image is provided. The method may include obtaining the medical image, and processing the medical image using a processing program. The processing program may include one or more optimized computation units. The one or more optimized computation units may be optimized by an instruction set supported by the at least one CPU. The instruction set may be configured to optimize at least one of an operation time of the processing program, a resource of the at least one CPU occupied by the processing program, and a count of instructions included in the processing program.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: June 7, 2022
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Wanli Teng, Yecheng Han, Yong E
  • Converting a stream of data using a lookaside buffer
    Patent number: 11347510
    Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 31, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Raymond Michael Zbiciak
  • Checking lock variables for transactions in a system with transactional memory support
    Patent number: 11347539
    Abstract: In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 31, 2022
    Assignee: Arm Limited
    Inventors: Matthew James Horsnell, Stephan Diestelhorst
  • Method for selectively connecting to a smart peripheral and system therefor
    Patent number: 11341075
    Abstract: A method may include a software service executing at an information handling system to determine desired capabilities of a docking station. The software service receives information from available docking stations via a wireless communication interface, the information identifying actual capabilities of each docking station. The method further includes coupling the information handling system to a selected docking station in response to determining at the information handling system that the actual capabilities of the selected docking station provide the desired capabilities.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Dell Products L.P.
    Inventors: Daniel L. Hamlin, Manuel Novoa, Vivek Viswanathan Iyer
  • Universal host and non-volatile memory express storage domain discovery for non-volatile memory express over fabrics
    Patent number: 11341074
    Abstract: In some examples, universal host and NVMe™ storage domain discovery for NVM Express™ over Fabrics (NVMe-oF™) may include broadcasting location parameters to a host and a plurality of NVMe™ storage domains for discovery of a NVM Express™ over Fabrics (NVMe-oF™) service. Based on host parameters and NVMe™ storage domain parameters received in response to the broadcast location parameters, the host and the NVMe™ storage domains may be respectively registered with the NVMe-oF™ service. A mapping that indicates a specified NVMe™ storage domain that is to communicate with the host may be obtained. Communication may be implemented between the host and the specified NVMe™ storage domain by forwarding the mapping and associated discovery target parameters to the host to implement discovery of the specified NVMe™ storage domain by the host, and connection of the specified NVMe™ storage domain to the host.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 24, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Krishna Babu Puttagunta, Rupin T. Mohan, Vivek Agarwal, Komateswar Dhanadevan, Dheeraj Sharma, Asutosh Satapathy
  • Defect repair circuits for a reconfigurable data processor
    Patent number: 11327771
    Abstract: A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 10, 2022
    Assignee: SambaNova Systems, Inc.
    Inventors: Gregory F. Grohoski, Manish K. Shah, Kin Hing Leung
  • Efficient resource upgrade
    Patent number: 11327655
    Abstract: In one implementation, a method includes establishing a connection between a new frontend system resource and an existing frontend system resource for a client network. The method further includes transferring, by a processing device, a frontend system resource role from the existing frontend system resource to the new frontend system resource to enable the existing frontend system resource to operate as a backend system resource.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 10, 2022
    Assignee: Pure Storage, Inc.
    Inventor: Peter E. Kirkpatrick
  • Mechanism to autonomously manage SSDS in an array
    Patent number: 11321249
    Abstract: Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oscar P. Pinto, Robert Brennan
  • Input/output device selection system
    Patent number: 11321250
    Abstract: An I/O device selection system includes a memory system, I/O devices that are coupled to the memory system; and an I/O scheduler that is coupled to the I/O devices. The I/O scheduler receives an I/O request that that is directed to the memory system, and determines at least one I/O operation that is configured to satisfy the I/O request. The I/O scheduler then identifies an operating level of the I/O devices that are configured to perform the at least one I/O operation and, based on the operating level of the I/O devices, selects a subset of the I/O devices for performing the at least one I/O operation, and transmits at least one I/O operation instruction that is configured to cause the subset of the I/O devices to perform the at least one I/O operation in order to satisfy the I/O request.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 3, 2022
    Assignee: Dell Products L.P.
    Inventors: Shyam Iyer, Srinivas Giri Raju Gowda, Anh Dinh Luong
  • Data processing apparatus and method
    Patent number: 11307864
    Abstract: The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: April 19, 2022
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Tianshi Chen, Lei Zhang, Shaoli Liu
  • Data processing apparatus and method
    Patent number: 11307866
    Abstract: The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: April 19, 2022
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Shaoli Liu, Shengyuan Zhou, Zidong Du
  • Memory device including processing circuit, and electronic device including system on chip and memory device
    Patent number: 11301399
    Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyuk Kwon, Nam Sung Kim, Kyomin Sohn, Jaeyoun Youn
  • Handling exceptions in a program
    Patent number: 11301249
    Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Albrecht Mayer, Neil Stuart Hastie, Pawel Jewstafjew
  • Processing system for dispatching tasks and memory access method thereof
    Patent number: 11301297
    Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU), a microcontroller, and a memory access unit. The AFU and the core share a plurality of virtual addresses to access a memory. The microcontroller is coupled between the core and the AFU. The core develops and stores a task in one of the virtual addresses. The microcontroller analyzes the task and dispatches the task to the AFU. The AFU accesses the virtual address indicating where the task is stored through the memory access unit to executes the task.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 12, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Neural processing unit (NPU) direct memory access (NDMA) memory bandwidth optimization
    Patent number: 11295205
    Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Jinxia Bai, Rosario Cammarota, Michael Goldfarb
  • Processing system for managing process and its acceleration method
    Patent number: 11294716
    Abstract: A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 5, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Wei Zhao, Xuehua Han, Fangfang Wu, Jin Yu
  • Systems and methods for calibrating devices using directed acyclic graphs
    Patent number: 11288073
    Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 29, 2022
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Andrew J. Berkley, Ilya V. Perminov, Mark W. Johnson, Christopher B. Rich, Fabio Altomare, Trevor M. Lanting
  • Electronic device, storage device, and disk device
    Patent number: 11289129
    Abstract: An electronic device according to one embodiment includes a housing, a first substrate, a second substrate, a first wireless communication device and a second wireless communication device. The first substrate is located inside the housing. The second substrate is located outside the housing and attached to the housing. The first wireless communication device is included in the first substrate. The second wireless communication device is included in the second substrate and wirelessly communicates with the first wireless communication device.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Taichi Okano, Nobuhiro Yamamoto, Kota Tokuda, Jia Liu, Masahide Takazawa