Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10204066
    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Eugenio Miluzzi, Marco Leo, Marco Castellano
  • Patent number: 10198183
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes at least one storage drive and at least one processing module coupled over a Peripheral Component Interconnect Express (PCIe) fabric. The data storage system includes a first processing module in a first storage assembly configured to receive a storage operation for a storage drive managed by a second processing module in a second storage assembly. The first processing module is configured to identify the second processing module as managing the storage drive associated with the storage operation and responsively transfer the storage operation over a tunneled network connection for handling by the second processing module of the second storage assembly.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 5, 2019
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Jason Breakstone
  • Patent number: 10185685
    Abstract: A serial communication branching device and a serial communication system are provided. The serial communication branching device, which branches a plurality of slaves connected to the master by a daisy chain into a plurality of paths, is equipped with a first communication circuit that carries out communication with the master connected to a preceding stage side, a plurality of second communication circuits that carry out communication with the slaves of the paths connected to a subsequent stage side, and a path selection circuit disposed between the first communication circuit and the second communication circuits. In the case that a slave connected on the subsequent stage side transmits a reply signal to the master responsive to a transmission signal transmitted from the master, the path selection circuit selects a path of the slave that transmits the reply signal, and outputs the reply signal from the selected path to the master.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 22, 2019
    Assignee: FANUC CORPORATION
    Inventors: Takahiro Baba, Kenichi Ito
  • Patent number: 10175996
    Abstract: A power and data housing assembly includes a housing body configured to retain and support an electronic device assembly in the form of an interactive display screen and associated electronics. The electronic device assembly is communicatively coupled to at least one peripheral device. The electronic device assembly is configured to provide interactive functions that include text messaging, time-keeping, calendar functions, calculations, game-playing, and audio/video media playback. The electronic device assembly is further configured to provide interactive control of and display of data from the at least one peripheral device. The electronic device is further configured to mirror a personal computing device's display on the electronic device assembly's display.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: January 8, 2019
    Inventors: Norman R. Byrne, Joseph D. Ward, Randell E. Pate
  • Patent number: 10176114
    Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 8, 2019
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Sam Idicula, Erik Schlanger, Rishabh Jain, Michael Duller
  • Patent number: 10169106
    Abstract: According to one or more embodiments, a system and computer implemented method for managing critical section processing are provided. The method includes generating, using a processor, a transaction scope for a process in response to processing in a critical section, collecting data related to the process, generating, using the processor, a request using the collected data, storing the request and data as a pending item in a private storage during critical section processing, and processing, using the processor, the request based on the transaction scope.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong L. Dos Reis, Christopher D. Filachek, Mei Hui Wang
  • Patent number: 10170165
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10162637
    Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Mikhail Plotnikov, Andrey Naraikin, Robert Valentine
  • Patent number: 10163468
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10162639
    Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Mikhail Plotnikov, Andrey Naraikin, Robert Valentine
  • Patent number: 10162638
    Abstract: Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Mikhail Plotnikov, Andrey Naraikin, Robert Valentine
  • Patent number: 10153012
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10153011
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10146730
    Abstract: The present disclosure illustrates a device for maintaining serial routing during request transmission and a method thereof. According to an embodiment, the device may select one of serial ports according to a routing rule to transmit a request. When not receiving the response, the corresponding routing data is deleted from the routing rule, and the device transmits the request through all serial ports, and upon receipt of the response, the device adds a piece of corresponding transaction data in the routing rule. As a result, the routing rule may be automatically updated when a new serial device is electrically connected to the gateway or the serial port through which the serial device is electrically connected to the gateway is changed. The technical effect that it is not necessary for the user to particularly set the gateway after installation may be achieved.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: December 4, 2018
    Assignee: MOXA INC.
    Inventors: Tsung-Hsien Lee, Chien-Ho Wang, Chih-Hung Yu
  • Patent number: 10146549
    Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee W. Howes, Benedict R. Gaster, Michael C. Houston
  • Patent number: 10141033
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10140237
    Abstract: A vehicle system includes a first communication path and a second communication path. The vehicle system further includes a processor programmed to determine a first communication speed associated with communicating over the first communication path and a secondary communication speed associated with communicating over the second communication path. The processor commands a first vehicle subsystem to communicate over the first communication path or the second communication path based at least in part on the first communication speed and the secondary communication speed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 27, 2018
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventor: Eric She
  • Patent number: 10127190
    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 13, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Michael D. Hutton, Anargyros Krikelis
  • Patent number: 10127175
    Abstract: An aircraft avionics system comprising rack mounted line replaceable units that exchange messages between them via a bus. The avionics system comprises a monitoring device arranged in the rack comprising a connector electrically linked to the bus and into which a rack mounted line replaceable unit is plugged, to be electrically linked to the bus. The monitoring device also monitors the messages exchanged, via the bus, between the line replaceable unit plugged into its connector and other units of the avionics system. The monitoring device comprises an acquisition unit to acquire signals transmitted or received by the line replaceable unit plugged into the connector during the exchange of messages with at least one other unit of the avionics system, for converting the signals into storable digital data and for assigning clock data to the data, and a storage unit for storing the storable digital data and the clock data.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 13, 2018
    Assignee: AIRBUS OPERATIONS SAS
    Inventors: Dominique Pronto, Lionel Deramond
  • Patent number: 10120819
    Abstract: An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Michael Rohleder, Stefan Singer, Josef Fuchs