Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10282330
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 7, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10275374
    Abstract: Disclosed herein is a method for controlling interrupts in an inverter. If a control unit checks that an interrupt is issued in main software while an inverter is operating, the control unit analyzes the type of the interrupt. The interrupt is converted into an interrupt ID sorted by functionality. If the interrupt ID is a previously registered interrupt ID, an interrupt function corresponding to the registered interrupt ID is executed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 30, 2019
    Assignee: LSIS CO., LTD.
    Inventor: Bong-Ki Lee
  • Patent number: 10268261
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Patent number: 10268628
    Abstract: A method includes parsing basic input/output system (BIOS) information to collect configuration attributes defining configurable features at an information handling system. A configuration attribute file is generated that includes the configuration attributes. The configuration attribute file is stored at a BIOS non-volatile random-access memory (NVRAM) at the information handling system and is accessible during initialization of the information handling system by BIOS instructions.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Dell Products, LP
    Inventors: Franklin Chuang, Xiaomei Miller
  • Patent number: 10268603
    Abstract: An electronic system may include a host, a memory, a data recording system, and a driving circuit. The driving circuit may drive a signal transferred between the host and the memory. The driving circuit may maintain amplitude and/or strength of the signal transferred between the host and the memory when the signal is monitored.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyung Kyu Kim, Il Hun Lee
  • Patent number: 10268602
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10268626
    Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 10261935
    Abstract: Provided are systems and methods for detecting excessive use of a peripheral device by host processes. In various implementations, a peripheral device can include an integrated circuit that includes a traffic counter. The traffic counter can increment based on events received by the peripheral device. The peripheral device can further include an integrated circuit device configured to associate the traffic counter with a process executing on a host device. The integrated circuit device can further initialize a rate counter for the process. When the rate counter reaches a pre-determined time limit, the integrated circuit device can determine that the process is exceeding a usage limit. The integrated circuit device can further read a value from the traffic counter to verify usage of the peripheral device by the process.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Leah Shalev, Nafea Bshara, Said Bshara
  • Patent number: 10248612
    Abstract: A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 2, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: James Henry Ross, Matthew Lee Banowetz
  • Patent number: 10248596
    Abstract: In accordance with embodiments of the present disclosure, a method may include receiving an input/output command from an application executing on a virtual machine of a hypervisor, wherein the hypervisor executes on a processor subsystem, determining if the input/output command meets a predefined criteria for trapping the input/output command, and responsive to determining that the input/output command meets a predefined criteria for trapping the input/output command, bypassing a storage stack of the hypervisor by passing the input/output command to an endpoint of an accelerator device assigned for access to the hypervisor.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 2, 2019
    Assignee: Dell Products L.P.
    Inventor: Shyam T. Iyer
  • Patent number: 10248468
    Abstract: A method to manage peripheral component interconnect (PCI) memory includes accessing a page table that includes mapped data representing base address register (BAR) space and addresses of PCI devices. The method also includes determining whether a requested address of a PCI device has a corresponding entry in the page table. The method further includes invoking a hypervisor to perform a memory operation to obtain address information of the PCI device upon determining that the requested address does not have the corresponding entry in the page table.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Charles S. Graham, Timothy J. Schimke
  • Patent number: 10241946
    Abstract: A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different virtual DMA channels and stored in a command queue structure, such that a first command sequence is processed to directly configure one or more first register descriptors at a context store to implement a direct configuration DMA mode for a first virtual channel, a second command sequence is processed to initiate a fetch of a linked list descriptor chain for loading one or more second register descriptors at a second DMA channel context store register to implement a link list configuration DMA mode for a second virtual channel, and a third command sequence is processed to retrieve an instruction program for loading into the command queue structure and execution by the DMA controller to implement a program configuration DMA mode for a third virtual channel.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael J. Rochford, Rabindra Guha, Daniel C. Laroche, Malcolm D. Stewart
  • Patent number: 10235077
    Abstract: Described is a technology by which an owner node in a server cluster maintains ownership of a storage mechanism through a persistent reservation mechanism, while allowing non-owning nodes read and write access to the storage mechanism. An owner node writes a reservation key to a registration table associated with the storage mechanism. Non-owning nodes write a shared key that gives them read and write access. The owner node validates the shared keys against cluster membership data, and preempts (e.g., removes) any key deemed not valid. The owner node also defends ownership against challenges to ownership made by other nodes, so that another node can take over ownership if a (formerly) owning node is unable to defend, e.g., because of a failure.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rajsekhar Das, David A. Dion
  • Patent number: 10234839
    Abstract: In an I/O module, a communication enables communications between first and second external devices upon a voltage being supplied from a power source thereto. A shutoff switch shuts off supply of the voltage to the communication controller when turned off. A capacitor is charged based on the voltage supplied from the voltage source while the shutoff switch is in an on state. The capacitor supplies an operating voltage to the communication controller while the shutoff switch is turned off. The communication controller detects a voltage across the capacitor as a diagnostic voltage, and outputs a turn-off command to the shutoff switch for turning off the shutoff switch. The communication controller determines whether there is a fixedly closed malfunction in the shutoff switch based on the diagnostic voltage while outputting the turn-off command to the shutoff switch.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 19, 2019
    Assignee: DENSO WAVE INCORPORATED
    Inventor: Takaaki Maekawa
  • Patent number: 10223120
    Abstract: Instructions and logic provide SIMD vector population count functionality. Some embodiments store in each data field of a portion of n data fields of a vector register or memory vector, at least two bits of data. In a processor, a SIMD instruction for a vector population count is executed, such that for that portion of the n data fields in the vector register or memory vector, the occurrences of binary values equal to each of a first one or more predetermined binary values, are counted and the counted occurrences are stored, in a portion of a destination register corresponding to the portion of the n data fields in the vector register or memory vector, as a first one or more counts corresponding to the first one or more predetermined binary values.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Terence Sych, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10216419
    Abstract: A system is described that includes a data bus communicatively coupled to a host processor, a graphics processing unit (GPU), and a data storage unit. The GPU is configured to receive instructions from the host processor to perform direct communication over the data bus with the data storage unit. Responsive to receiving instructions to communicate directly with the data storage unit, the GPU will initiate a direct communication channel over the data bus. Once established, a direct communications channel allows the data storage unit and the GPU to directly exchange information and bypass the host CPU and system memory.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: February 26, 2019
    Assignee: HGST Netherlands B.V.
    Inventor: Arup De
  • Patent number: 10216673
    Abstract: Communications are intercepted between a universal serial bus (USB) device and a host, at least by implementing first device firmware of the USB device. The USB device contains its own second device firmware. Using at least the implemented first device firmware, intercepted communications from the USB device toward the host are sanitized. The sanitizing is performed so that no communication from the USB device is directly forwarded to the host and instead only sanitized communications are forwarded to the host. Methods, apparatus, and computer program products are disclosed.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anton Beitler, Jiyong Jang, Dhilung Hang Kirat, Anil Kurmus, Matthias Neugschwandtner, Marc Philippe Stoecklin
  • Patent number: 10216675
    Abstract: A technique for establishing a network interface and an external interface in a connector is disclosed. A personal computer (PC) includes a device controller for controlling data transmission with a peripheral device and a network device, and a receptacle including multiple pins for connecting data channels of the device controller to the peripheral device through the external interface and the network device through the network interface. The PC further includes a crossbar switch for switching the data channels to establish the external interface and the network interface in the receptacle. The external interface complies with the USB standards, and the network interface complies with the Ethernet standards.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 26, 2019
    Assignee: LENOVO (SINGAPORE) PTE LTD
    Inventors: Yasumichi Tsukamoto, Luis Antonio Hernandez, Tomoki Harada, Daisuke Watanabe
  • Patent number: 10209988
    Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine
  • Patent number: 10210116
    Abstract: In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Michael Kevin Batenburg, Vincent Pierre Le Roy, Praveen Kumar Origanti