Patents Examined by Cheung Lee
  • Patent number: 11508621
    Abstract: A semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shahaji B. More
  • Patent number: 11508902
    Abstract: A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi Heng Tsai, Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng
  • Patent number: 11508850
    Abstract: A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300┬░.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoki Okuno, Tetsuya Kakehata, Hiroki Komagata, Yuji Egi
  • Patent number: 11502086
    Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: November 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Son, Jae Hoon Kim, Kwang-Ho Park, Seungjae Jung
  • Patent number: 11502249
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 15, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Patent number: 11495601
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain; the transistor and the capacitor are placed to be embedded in the interlayer film. Below the semiconductor layer, one of the source and the drain is in contact with the electrode. Above the semiconductor layer, the other of the source and the drain is in contact with one electrode of the capacitor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takanori Matsuzaki, Ryo Tokumaru, Ryota Hodo
  • Patent number: 11495709
    Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone is disposed around a center of the substrate. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 8, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Kuang-Yuan Hsu, Chien-Chih Yen, Yen-Lin Lai, Shen-Jie Wang, Sheng-Yuan Sun
  • Patent number: 11495738
    Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance├Śarea (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Vignesh Sundar, Yu-Jen Wang, Luc Thomas, Guenole Jan
  • Patent number: 11495500
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Hans-Joachim Gossmann
  • Patent number: 11489076
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 11488874
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Patent number: 11488869
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Keng-Chu Lin, Yu-Yun Peng
  • Patent number: 11489077
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Patent number: 11488997
    Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: November 1, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11488826
    Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: November 1, 2022
    Assignee: IMEC vzw
    Inventors: Boon Teik Chan, Yong Kong Siew, Juergen Boemmels
  • Patent number: 11482610
    Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen, Chih-Hsuan Chen
  • Patent number: 11482622
    Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan, Christopher Jezewski, Ashish Agrawal
  • Patent number: 11482623
    Abstract: Provided are a thin film transistor array substrate and an electronic device including the same. More specifically, the thin film transistor array includes a first active layer including a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area, a first gate electrode disposed on the first active layer, and a second gate electrode disposed on the same layer as the first gate electrode to overlap one end of the first gate electrode and to which a signal corresponding to a signal applied to the first gate electrode is applied. Therefore, it is possible to have a structure for simultaneously controlling the threshold voltage, mobility, and subthreshold (S) parameter of a thin film transistor.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: October 25, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: JuHeyuck Baeck, Dohyung Lee, ChanYong Jeong
  • Patent number: 11482641
    Abstract: A method for manufacturing an electronic device includes providing a substrate, forming a plurality of connecting pads and a plurality of conductive portions partially overlapped by the plurality of connecting pads on a surface of the substrate; forming a plurality of conductive lines on the substrate, wherein the plurality of conductive lines are electrically connected to the plurality of conductive portions; and bonding a plurality of light emitting units to the plurality of connecting pads. The method may further includes identifying a defective light emitting unit from the plurality of light emitting units; removing the defective light emitting unit from a corresponding position on the substrate; and bonding-another light emitting unit to the corresponding position.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: October 25, 2022
    Assignee: InnoLux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai
  • Patent number: 11476259
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills