Patents Examined by Cheung Lee
  • Patent number: 10714565
    Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-hyung Nam, Bong-Soo Kim, Yoosang Hwang
  • Patent number: 10714461
    Abstract: The present invention relates to an electronic unit having at least one first electronic component and one second electronic component that are fastened to a substrate. A shielding is arranged between the first and second electronic components that comprises an elevated portion that projects from a plane defined by the substrate or that extends from its surface, that acts as a shielding and that is formed in one piece with the substrate.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 14, 2020
    Assignee: VISHAY SEMICONDUCTOR GMBH
    Inventors: Christoph Paul Gebauer, Alexander Kamay
  • Patent number: 10705766
    Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10707210
    Abstract: Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Fredrick D. Fishburn
  • Patent number: 10707240
    Abstract: The purpose of the invention is to countermeasure a disconnection between the drain electrode or the source electrode and the wiring or the electrode formed on the insulating film via through hole. The concrete structure is that: A display device having a display area including a plurality of pixels comprising: the pixel includes a thin film transistor having a semiconductor layer as an active element, a first insulating film is formed to cover a drain electrode of the thin film transistor, the drain electrode is connected with an electrode or an wiring that are formed on the first insulating film via a through hole, an oxide semiconductor layer exists between the drain electrode and the first insulating film, the oxide semiconductor layer does not exist at the bottom of the through hole.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Japan Display Inc.
    Inventor: Manabu Yamashita
  • Patent number: 10707238
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 10700029
    Abstract: A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 30, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10692709
    Abstract: A method of analyzing a complex sample includes performing a sequential chromatographic-IMS-MS analysis of a sample to obtain a plurality of experimental mass spectra having isotopic clusters, wherein each spectrum of the plurality of spectra is associated with a chromatographic retention time and an ion-mobility drift time. The method also includes calculating a model isotopic cluster of a precursor or product ion associated with a candidate compound in the sample, in correspondence to the natural isotopic-abundance ratios of elements composing the compound. The method further includes comparing peaks of the model isotopic cluster to corresponding peaks of an isotopic cluster of one of the experimental mass spectra to extract one or more saturated or interfered peaks of the experimental isotopic cluster, wherein at least one of the peaks of the experimental isotopic cluster is un-saturated and un-interfered.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Waters Technologies Corporation
    Inventors: Scott J. Geromanos, Marc V. Gorenstein, Daniel Golick, Steven J. Ciavarini
  • Patent number: 10692967
    Abstract: A self-routing capacitor for an integrated circuit having: a first electrode comprising a first base region and a first finger, the first finger extending from a wall of the first base region in a first direction; a second electrode comprising a second base region and a second finger; the second finger extending from a wall of the second base region in a second direction substantially parallel to and opposing the first direction, the second finger coupled to the first finger; a third electrode comprising a third base region and a third finger, the third finger extending from a first wall of the third base in the second direction; and a fourth electrode comprising a fourth finger, the fourth finger extending from a second wall of the third base region in the first direction. The capacitor being coupled to other metal layers through a base region of an electrode.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 23, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Baozhen Chen, Lalinda D. Fernando, Micah Galletta O'Halloran, Andrew Wayne Shaw
  • Patent number: 10693058
    Abstract: A magnetic tunnel junction device and a magnetic memory device. The magnetic tunnel junction device includes a magnetic tunnel junction including a fixed magnetic body, an insulator, and a free magnetic body sequentially stacked and a conducting wire disposed adjacent the free magnetic body of the magnetic tunnel junction to apply in-plane current. The fixed magnetic body has a fixed magnetization direction and is a thin film including a material magnetized directionally perpendicular to a film surface. The free magnetic body has a structure of [auxiliary free magnetic layer/free non-magnetic layer]N/main free magnetic layer, where N is a positive integer greater than or equal to 2 and indicates that an [auxiliary free magnetic layers/free non-magnetic layers] structure is stacked repeatedly N times.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 23, 2020
    Assignee: Korea University Research and Business Foundation
    Inventor: Kyung-Jin Lee
  • Patent number: 10692770
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10686095
    Abstract: A photoelectric sensor including at least any one of a light projecting unit for emitting light and a light receiving unit for detecting light includes a substrate on which at least any one of the light projecting unit and the light receiving unit is mounted, a cover which has a protecting portion facing the substrate and for protecting the substrate and a side wall extending from a periphery of the protecting portion, and a sealing member which seals at least any one of the light projecting unit and the light receiving unit that is mounted on the substrate, in which the cover has a protruding portion on a surface which is positioned outside a side surface of the substrate and intersects an extending direction of the side wall, and the protruding portion is in contact with the sealing member.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 16, 2020
    Assignee: OMRON Corporation
    Inventors: Hiroyuki Mizusaki, Makoto Sugimoto, Jumpei Nakamura, Tomohiro Tsuji
  • Patent number: 10679977
    Abstract: A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Patent number: 10672735
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 2, 2020
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, Wei Qin
  • Patent number: 10672797
    Abstract: The array substrate includes: a substrate; a gate electrode; a gate insulating layer; an active layer; a source-drain electrode; a passivation layer; a pixel electrode; the active layer includes a first silicon layer, and the first silicon layer disposed below the channel is composed of polycrystalline silicon, and the remaining part of the first silicon layer is composed of amorphous silicon.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 2, 2020
    Assignees: CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD., HKC CORPORATION LIMITED
    Inventor: Chuan Wu
  • Patent number: 10665680
    Abstract: A silicon carbide semiconductor assembly and a method of forming a silicon carbide (SiC) semiconductor assembly are provided. The silicon carbide semiconductor assembly includes a semiconductor substrate and an electrode. The semiconductor substrate is formed of silicon carbide and includes a first surface, a second surface opposing the first surface, and a thickness extending therebetween. The method includes forming one or more electronic devices on the first surface and thinning the semiconductor substrate by removing the second surface to a predetermined depth of semiconductor substrate and leaving a third surface opposing the first surface. The method further includes forming a non-ohmic alloy layer on the third surface at a first temperature range and annealing the alloy layer at a second temperature range forming an ohmic layer, the second temperature range being greater than the first temperature range.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Microsemi Corporation
    Inventors: Bruce Odekirk, Jacob Alexander Soto
  • Patent number: 10665822
    Abstract: A display screen, a manufacturing method thereof, and a display device are disclosed. The display screen includes a base substrate, a thin film transistor located on the base substrate, the thin film transistor including a metal layer, at least one of a light-absorbing material layer or a scattering structure disposed between the base substrate and the metal layer in a direction perpendicular to the base substrate.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: May 26, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guanghui Liu, Dongfang Wang
  • Patent number: 10665631
    Abstract: A display panel includes an array substrate and a color film substrate. The array substrate includes a plurality of light-sensing elements. The color film substrate includes a first substrate, a first light-shielding layer, and at least one second light-shielding layer. The first light-shielding layer is located on a side of the first substrate adjacent to the array substrate, and includes a plurality of first hollowed regions. The at least one second light-shielding layer is located on a side of the first light-shielding layer adjacent to the array substrate, and includes a plurality of second hollowed regions. In a direction perpendicular to the first substrate, orthogonal projections of the plurality of first hollowed regions, the plurality of second hollowed regions, and the plurality of light-sensing elements overlap with each other. A first flat layer is disposed between the first light-shielding layer and the at least one second light-shielding layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 26, 2020
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Xuanxian Cai, Bozhi Liu, Guozhao Chen
  • Patent number: 10651299
    Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity-type drift region; a transistor portion; and a diode portion, wherein the transistor portion and the diode portion each have: a second conductivity-type base region; a plurality of trench portions penetrating the base region and having conductive portions provided therein; and a mesa portion sandwiched by trench portions, the transistor portion has one or more first conductivity-type accumulation regions that have doping concentrations higher than that of the drift region, the diode portion has one or more first conductivity-type high concentration regions that have doping concentrations higher than that of the drift region, and an integrated concentration of the doping concentrations of the accumulation regions is higher than an integrated concentration of the doping concentrations of the one or more high concentration regions of the mesa portion of the diode portion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10651313
    Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Matthew V. Metz, Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Sean T. Ma