Abstract: A thin film transistor and a display device comprising the same are provided. The thin film transistor comprises a first gate electrode and a second gate electrode, which are spaced apart from each other to overlap each other, and an active layer disposed between the first gate electrode and the second gate electrode, including a first active layer and a second active layer, wherein the active layer includes a channel portion, a first connection portion that is in contact with one side of the channel portion, and a second connection portion that is in contact with the other side of the channel portion. The channel portion includes a first channel portion and a second channel portion, which are disposed in parallel.

Abstract: A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.

Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Abstract: A method of manufacturing an integrated circuit (IC) includes providing a structure having a fin over a substrate in a region of the IC, a sacrificial gate stack engaging a channel region of the fin, and gate spacers on sidewalls of the sacrificial gate stack. The first layers and the second layers are alternately stacked over the substrate. The method also includes etching the fin adjacent the gate spacers, resulting in source/drain trenches, partially recessing the second layers exposed in the source/drain trenches, resulting in gaps between adjacent layers of the first layers in the fin, depositing inner spacer features in the gaps in the fin, epitaxially growing source/drain features in the source/drain trenches, and replacing the sacrificial gate stack with a metal gate stack. The metal gate stack includes a gate dielectric layer disposed over top and sidewalls of the fin having both the first and the second layers.

Abstract: A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: An imaging device including a photoelectric convertor that includes a first electrode, a second electrode, and a photoelectric conversion layer located between the first electrode and the second electrode. The photoelectric convertor has a photoelectric conversion characteristic in which a rate of change of the photoelectric conversion efficiency of the photoelectric convertor with respect to a first bias voltage between the first electrode and the second electrode when the first bias voltage is in a first voltage range, is greater than the rate of change with respect to a second bias voltage when the second bias voltage is in a second voltage range that is higher than the first voltage range, and a first voltage is applied to the first electrode or the second electrode so that a bias voltage between the first electrode and the second electrode exists in the first voltage range.

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: Aspects of the disclosure include light-emitting diodes (LEDs) formed without phosphor deformation during the lamination process. An exemplary method can include forming one or more LEDs on a backplane and forming a protective layer on the backplane. The protective layer can be patterned to define one or more trenches exposing sidewalls of a respective one LED of the one or more LEDs and a surface of the backplane. Each trench can be filled with a color-shifting coating. The method includes laminating the one or more LEDs, the backplane, the protective layer, and the color-shifting coating between one or more inner reinforcing layers and one or more outer layers to define a display.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

Abstract: A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.

Abstract: A display apparatus can include a buffer layer on a flexible substrate; a first thin film transistor on the buffer layer including a first semiconductor pattern, a first gate electrode, a first source electrode and a first drain electrode, a second thin film transistor including a second semiconductor pattern, a second gate electrode, a second source electrode and a second drain electrode, and a passivation layer on the first and the second thin film transistors. Also, the display apparatus includes a planarization layer, a light-emitting device including a first electrode, a light-emitting layer and a second electrode on the planarization layer, and an encapsulating element on the light-emitting device. Also, the light-emitting device is electrically connected to the first thin film transistor, the first semiconductor pattern includes silicon, and the second semiconductor pattern includes an oxide semiconductor pattern, and the second gate electrode includes lower and upper electrodes.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.