Abstract: The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.

Abstract: Display panel and display device are provided. The display panel includes: a non-display area including a first non-display area and a second non-display area oppositely arranged along a first direction, and a third non-display area and a fourth non-display area oppositely arranged along a second direction, the first direction intersecting the second direction; a first electrode connection structure at least in the third non-display area and/or the fourth non-display area; and a first area running through the display panel along the first direction, and the first electrode connection structure being outside the first area.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: A semiconductor package includes a first package substrate having a first area and a second area that is distinct and separate from the first area, a first connection element disposed on the first area and having a first thickness, a first semiconductor chip connected to the first connection element, a second connection element disposed on the second area and having a second thickness that is greater than the first thickness, a third connection element disposed on the second connection element and electrically connected to the second connection element, a second package substrate disposed on the third connection element, and a second semiconductor chip disposed on the second package substrate.

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

Abstract: Structures and corresponding methods of fabrication for ICs having fins and/or vertical nanosheets made by forming and etching a porous semiconductor (?-Semi) from a crystalline semiconductor. Embodiments include FinFETs and “gate-all-around” FETs. Such FET structures may be made by patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a fin or nanosheet; converting the outlined regions to ?-Semi having essentially vertical walls; further converting the outlined regions to ?-Semi having flared walls; then selecting one of these options: etching the ?-Semi to define fins, etching the ?-Semi to define nanosheets with a residual ?-Semi floor, or etching the ?-Semi to define nanosheets with no residual ?-Semi floor; and forming a gate structure over the fins or around the nanosheets. Additional steps and structures (e.g., formation of source and drain regions, formation of contacts, metallization layers, vias, etc.) may then be performed.

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.

Abstract: A method of processing a substrate includes forming an amorphous silicon (a-Si) layer over the substrate, where the substrate includes a dielectric layer and a conductive layer, and the a-Si liner covers a surface of the dielectric layer and a surface of the conductive layer. The method includes converting the a-Si liner into a silicon-containing layer including a metal; and depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, where the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.

Abstract: A device structure includes a substrate, a fin structure disposed on the substrate and elongated in an X direction, a gate structure formed on the fin structure and elongated in a Y direction transverse to the X direction to terminate at two opposite ends, at least one dielectric portion connected to at least one of the two opposite ends of the gate structure, and having two sides that are opposite to each other in the X direction, and a pair of gate spacers which are spaced apart from each other in the X direction and are respectively disposed on two lateral sides of the gate structure, and which are elongated in the Y direction to cover the two sides of the dielectric portion, respectively. A method for manufacturing the device structure is also disclosed.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. The method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. The first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. The method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

Abstract: A method for forming a stacked transistor device is disclosed, in which a nanosheet field-effect transistor (FET) structure and a fin FET structure are formed. The method comprises forming a first fin structure and a second fin structure from a vertical stack, wherein the second fin structure is arranged above the first fin structure, and wherein the vertical stack comprises a middle layer arranged between the first and second fin structures. The method further comprises forming, from above, a gate structure across a channel region of the second fin structure, forming, from below, a gate structure across a channel region of the first fin structure, and forming source and drain regions for the first and second fin structures.

Abstract: A display panel and a display device. The display panel includes a power supply high-voltage signal line, a driving thin film transistor, and a light emitting element. The driving thin film transistor comprises an active layer. The active layer includes a source region, a drain region, and a channel region. The source region is connected to the power supply high-voltage signal line. The drain region is connected to the light emitting element. A part of the channel region close to the drain region has a lower majority carrier concentration than a part of the channel region close to the source region.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package including a first redistribution layer, at least one chip and a second redistribution layer, and at least one second package disposed on the first package and including a substrate, an adhesive layer, at least two optical chips, an encapsulant layer, and a third redistribution layer. The optical chips are attached to a surface of the substrate close to the first package through the adhesive layer, and each optical chip has an optical surface close to the substrate. The encapsulant layer is disposed on the surface and surrounds the optical chips. The third redistribution layer is disposed between the encapsulant layer and the second redistribution layer, in which the second redistribution layer is electrically connected to the optical chips through the third redistribution layer.

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a first channel oriented in a first direction and connected to a ground reference voltage level provided by a backside metal layer. The Cross FETs also use a second device, such as the p-type device, having a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by a frontside metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer in order to be placed between the backside metal layer and the source region of an n-type device. The power connections reduce on-die area, reduces semiconductor fabrication complexity, which improves wafer yield, and reduces voltage droop, which increases performance.

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method includes forming a stack over a substrate and patterning the stack and a portion of the substrate to form a fin-shaped structure comprising a base portion formed from the substrate and a top portion formed from the stack. The stack includes channel layers interleaved by sacrificial layers and two-dimensional (2D) material layers disposed between adjacent ones of the channel layers and the sacrificial layers. The method also includes selectively removing the sacrificial layers of the top portion to form a plurality of channel members disposed over the base portion, forming a first gate structure and a second gate structure above the first gate structure. The first gate structure wraps around a bottom portion of the channel members. The second gate structure wraps around a top portion of the channel members.