Patents Examined by Cheung Lee
  • Patent number: 11043523
    Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors and alignment marks; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 22, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11043504
    Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: June 22, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Shaokang Yao, Xiaohua Ju, Guanqun Huang
  • Patent number: 11043574
    Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 22, 2021
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferdinando Iucolano, Paolo Badala'
  • Patent number: 11037993
    Abstract: A detection device according to an embodiment of the present disclosure includes a plurality of semiconductor layers, each including a plurality of electrode regions and a semiconductor region. The plurality of electrode regions are: arranged at intervals in a cross direction crossing a thickness direction; configured to generate electric charges by a photoelectric effect of irradiation of radiation; and configured to produce an electric field in the cross direction by voltage application. The semiconductor region is provided at least between the electrode regions adjacent to one another in the cross direction. The plurality of semiconductor layers are stacked in the thickness direction.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 15, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kohei Nakayama, Fumihiko Aiga, Atsushi Wada, Isao Takasu, Yuko Nomura, Sara Yoshio, Rei Hasegawa
  • Patent number: 11024801
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 1, 2021
    Inventors: Jung-Tang Wu, Jui-Hung Ho, Chin-Szu Lee, Meng-Yu Wu, Szu-Hua Wu
  • Patent number: 11024772
    Abstract: Provided is a light emitting diode. The light emitting diode includes a substrate, a first semiconductor layer on the substrate, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a conductor passing through the second semiconductor layer and the active layer to contact the first semiconductor layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 1, 2021
    Assignee: KOREA POLYTECHNIC UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventors: Sung-Nam Lee, Seung-Hye Baek
  • Patent number: 11018260
    Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yao-Jen Yang, Yih Wang
  • Patent number: 11011372
    Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Peng, Te-Yang Lai, Sai-Hooi Yeong, Chi On Chui
  • Patent number: 11004863
    Abstract: A non-volatile memory having a gate all around thin film transistor includes a multi-layer structure, an elongated plug structure, a first conductive plug, and a second conductive plug. The multi-layer structure includes a plurality of gate electrode layers stacked on a substrate separately from each other. The elongated plug structure penetrates through the multi-layer structure, and a cross-section of the elongated plug structure has an elongated contour. The elongated plug structure includes an insulating pillar, a channel layer, and a gate dielectric layer. The channel layer surrounds the insulating pillar. The gate dielectric layer surrounds the channel layer. The gate electrode layers surround the gate dielectric layer. The first conductive plug is disposed between the channel layer and the substrate and between the insulating pillar and the substrate. The second conductive plug is disposed on the insulating pillar and is covered by the channel layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Zusing Yang
  • Patent number: 11005040
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage layer. A top electrode overlies a bottom electrode. The data storage layer is disposed between the top and bottom electrodes. The data storage layer has a first region and a second region. The first region comprises a first material and the second region comprises a compound of the first material and a reactive species.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Yu, Jau-Yi Wu
  • Patent number: 11005018
    Abstract: A semiconductor continuous array layer comprising: an array of multiple semiconductor units; a sidewall of each semiconductor unit is surrounded by a semi-cured material or a cured material connecting the semiconductor units together to form a semiconductor continuous array; wherein multiple voids or air gaps are enclosed by the semi-cured material or the cured material within the semiconductor continuous array or around the edge of the semiconductor continuous array.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 11, 2021
    Inventor: Chen-Fu Chu
  • Patent number: 10998374
    Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.
    Type: Grant
    Filed: December 5, 2020
    Date of Patent: May 4, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Patent number: 10991785
    Abstract: A double-sided display panel and a method of fabricating the same are provided. The double-sided display panel is an organic light emitting diode (OLED) device with two structures of bottom emission and top emission on a single thin film transistor (TFT) substrate. An OLED display mode combines two different driving structures of active matrix organic light emitting diodes and passive matrix organic light emitting diodes, such that an OLED display realizes double-sided display performance, and has a high-resolution performance on one side and a basic display performance on another side.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: April 27, 2021
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Weijing Zeng
  • Patent number: 10985255
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghwan Huh, Dongchan Kim, Dae Hyun Kim, Euiju Kim, Jisoo Lee
  • Patent number: 10978501
    Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 13, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10978424
    Abstract: A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically connected to the first integrated circuit component. The third integrated circuit component is stacked on and electrically connected to the second integrated circuit component. The dielectric encapsulation laterally encapsulates the second integrated circuit component or the third integrated circuit component. In addition, manufacturing methods of the above-mentioned semiconductor device are provided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 10978599
    Abstract: Provided is a method for improving the corrosion resistance of a gold finger, which is applicable to an electro-optical circuit board including gold fingers, wherein a guide line is arranged at a root portion of the gold fingers of the electro-optical circuit board. The method comprises the following steps in sequence: 1) electrical connection: using an outer lead to electrically connect all gold fingers of a electro-optical circuit board; 2) solder resistance: performing solder resistance on an area other than the outer lead; 3) gold plating on the gold fingers; 4) etching of the outer lead; and 5) solder resistance: performing solder resistance on a vacancy after etching of the lead. In the method, an outer lead is arranged to electrically connect all gold fingers of a electro-optical circuit board, so that all sides of the gold fingers are plated with gold, thereby significantly improving the corrosion resistance of the gold fingers.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignees: Guangzhou Fastprint Circuit Tech Co., Ltd., Shenzhen Fastprint Circuit Tech Co., Ltd., Guanazhou Fastorint Electronic Co., Ltd.
    Inventors: Liyang Chen, Shuxiao Qiao
  • Patent number: 10978579
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 13, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 10971628
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature over a substrate and a fin structure protruding from the substrate and partially surrounded by the isolation feature. The fin structure includes a first portion above the isolation feature and having a first width. The fin structure also includes a second portion extending from a top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile. The semiconductor device structure also includes a gate structure covering the first portion and the second portion of the fin structure.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Neng Lin, Shian-Wei Mao
  • Patent number: 10971355
    Abstract: A substrate includes a ceramic core, a first adhesion layer, a barrier layer, and a second adhesion layer. The first adhesion layer encapsulates the ceramic core and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio. The barrier layer encapsulates the first adhesion layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio. The second adhesion layer encapsulates the barrier layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 6, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kwang-Ming Lin, Yung-Fong Lin