Abstract: A display panel including a driving circuit layer, multiple light emitting devices and multiple encapsulation structures is provided. Each of the light emitting devices includes a first electrode, a light emitting pattern, a second electrode and a pixel definition layer. The light emitting pattern is disposed on the first electrode. The second electrode is disposed on the light emitting pattern. The pixel definition layer is disposed on the driving circuit layer. The light emitting pattern and the second electrode cover the pixel definition layer, and the first electrode located in a pixel opening of the pixel definition layer. The encapsulation structures cover the light emitting devices and each includes a first encapsulation pattern. Edges of the first encapsulation pattern, the light emitting pattern and the second electrode overlapping with each other are aligned with each other.

Abstract: A method of manufacturing a display device is disclosed that includes sequentially forming a display panel and an encapsulation layer on a first surface of a substrate; forming a first protective layer covering the encapsulation layer, forming a second protective layer covering the first protective layer; forming a first film on the first surface of the substrate; removing a second surface of the substrate facing the first surface; removing the first film and the second protective layer; and after removing the first film and the second protective layer, removing the first protective layer.

Abstract: According to one embodiment, a semiconductor device includes a base, a first circuit board provided on the base, a second circuit board provided on the base at a certain interval from the first circuit board, a first connector provided with a first wire that is bridged between an upper surface of the first circuit board and an upper surface of the second circuit board to connect the two boards, and a first ferrite arranged on the base and directly below the first wire between the first circuit board and the second circuit board.

Abstract: Described herein are devices that relate to sensor, data, and interactive interfaces between micro or nano electronics and biofilms, which optionally include an added extracellular matrix. Biofilms in the interfaces can include adherent cells or microorganisms, for example, fungi, bacteria, and the biofilms may include viruses. Computational capability, circuitry, and methods are provided for interactive measurements/processing between the electronics and biofilms.

Abstract: The present disclosure provides a display panel and an electronic device. A pixel definition layer of the display panel is provided with multiple second openings corresponding to multiple light-sensing sensors, a metal inhibition layer of the display panel is laid in the multiple second openings, and a encapsulation layer of the display panel is disposed to cover the metal inhibition layer and fill into the multiple second openings. By providing the multiple second openings on the pixel definition layer, lights are capable of passing through the pixel definition layer to reach the multiple light-sensing sensors, thereby solving a problem that an existing under-screen optical fingerprint is difficult to be directly applied in OLED products.

Abstract: In a liquid printing method, a second workpiece is applied onto a first workpiece. A metal on the second workpiece contacts a dielectric on the first workpiece thereby forming an alloyed oxide film. This can be used to form a liquid metal printed 2D alloyed oxide film transistor. The alloyed oxide film can be InOx or other materials.

Abstract: A package for an integrated circuit die (e.g., a chip). A routing layer is layered between the chip and package contacts of the package. The chip has a planar surface along which the chip includes die contacts. The routing layer lies along the planar surface of the chip, and electrically connects the die contacts of the chip to the package contacts of the package. This allows the chip, the routing layer, and the package contacts to be stacked together to form a relatively thin, compact package. The routing layer connects the die contacts of the chip to the package contacts of the package, such that the die contacts need not have the same layout as the package contacts, thus allowing packages with the same package contact layouts to be used to package chips with varying die contact layouts. A lead in conductive contact with the package contact.

Abstract: An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.

Abstract: A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a step back side; a second substrate comprising a cavity, wherein the integrated device is located at least partially in the cavity of the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer is located at least partially in the cavity of the second substrate.

Abstract: The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.

Abstract: Display panel and display device are provided. The display panel includes: a non-display area including a first non-display area and a second non-display area oppositely arranged along a first direction, and a third non-display area and a fourth non-display area oppositely arranged along a second direction, the first direction intersecting the second direction; a first electrode connection structure at least in the third non-display area and/or the fourth non-display area; and a first area running through the display panel along the first direction, and the first electrode connection structure being outside the first area.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: A semiconductor package includes a first package substrate having a first area and a second area that is distinct and separate from the first area, a first connection element disposed on the first area and having a first thickness, a first semiconductor chip connected to the first connection element, a second connection element disposed on the second area and having a second thickness that is greater than the first thickness, a third connection element disposed on the second connection element and electrically connected to the second connection element, a second package substrate disposed on the third connection element, and a second semiconductor chip disposed on the second package substrate.

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

Abstract: Structures and corresponding methods of fabrication for ICs having fins and/or vertical nanosheets made by forming and etching a porous semiconductor (?-Semi) from a crystalline semiconductor. Embodiments include FinFETs and “gate-all-around” FETs. Such FET structures may be made by patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a fin or nanosheet; converting the outlined regions to ?-Semi having essentially vertical walls; further converting the outlined regions to ?-Semi having flared walls; then selecting one of these options: etching the ?-Semi to define fins, etching the ?-Semi to define nanosheets with a residual ?-Semi floor, or etching the ?-Semi to define nanosheets with no residual ?-Semi floor; and forming a gate structure over the fins or around the nanosheets. Additional steps and structures (e.g., formation of source and drain regions, formation of contacts, metallization layers, vias, etc.) may then be performed.

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

Abstract: A method of processing a substrate includes forming an amorphous silicon (a-Si) layer over the substrate, where the substrate includes a dielectric layer and a conductive layer, and the a-Si liner covers a surface of the dielectric layer and a surface of the conductive layer. The method includes converting the a-Si liner into a silicon-containing layer including a metal; and depositing the metal over the silicon-containing layer using the silicon-containing layer as a seed layer for the depositing, where the metal deposited over the silicon-containing layer and the conductive layer are electrically connected.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.

Abstract: A device structure includes a substrate, a fin structure disposed on the substrate and elongated in an X direction, a gate structure formed on the fin structure and elongated in a Y direction transverse to the X direction to terminate at two opposite ends, at least one dielectric portion connected to at least one of the two opposite ends of the gate structure, and having two sides that are opposite to each other in the X direction, and a pair of gate spacers which are spaced apart from each other in the X direction and are respectively disposed on two lateral sides of the gate structure, and which are elongated in the Y direction to cover the two sides of the dielectric portion, respectively. A method for manufacturing the device structure is also disclosed.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.