Patents Examined by Cheung Lee
  • Patent number: 10256287
    Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 9, 2019
    Assignee: pSemi Corporation
    Inventors: Eric S. Shapiro, Matt Allison
  • Patent number: 10243102
    Abstract: Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a light-emitting diode (LED) includes a substrate, a carrier confinement (CC) region positioned over the substrate, and an active region positioned over the CC region. The CC region includes a first CC layer comprising indium gallium phosphide and a second CC layer positioned over the first CC layer. The second CC layer includes gallium arsenide phosphide. The active region is configured to have a transient response time of less than 500 picoseconds (ps).
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 26, 2019
    Assignee: LUMEOVA, INC.
    Inventors: Mohammad Ali Khatibzadeh, Arunesh Goswami
  • Patent number: 10243007
    Abstract: An array substrate, a display panel and display device including the array substrate, and a method of manufacturing the array substrate are provided. The array substrate includes a display area, a plurality of first transistors disposed in the display area, a non-display area disposed at a periphery of the display area and a plurality of second transistors disposed in the non-display area, wherein compared to the plurality of first transistors, an active layer of each second transistor has a smaller thickness.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jilei Gao, Jing Sun, Jinliang Liu, Hongqiang Luo, Zuwen Liu
  • Patent number: 10236308
    Abstract: A thin film transistor includes a first blocking layer disposed on a substrate, and an active pattern disposed on the first blocking layer. The active pattern includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The thin film transistor further includes a gate electrode disposed on the active pattern. The channel region corresponds to a portion of the active pattern overlapped by the gate electrode. The thin film transistor additionally includes a source electrode connected to the source region, and a drain electrode connected to the drain region. The active pattern includes a first part and a second part. The first part partially overlaps with the first blocking layer, and the first part and the second part have different thicknesses from each other.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Hee Lee, In Jun Bae
  • Patent number: 10236306
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 10236349
    Abstract: A p-type oxide which is amorphous and is represented by the following compositional formula: xAO.yCu2O where x denotes a proportion by mole of AO and y denotes a proportion by mole of Cu2O and x and y satisfy the following expressions: 0?x<100 and x+y=100, and A is any one of Mg, Ca, Sr and Ba, or a mixture containing at least one selected from the group consisting of Mg, Ca, Sr and Ba.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 19, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Yukiko Abe, Naoyuki Ueda, Yuki Nakamura, Shinji Matsumoto, Yuji Sone, Mikiko Takada, Ryoichi Saotome
  • Patent number: 10236330
    Abstract: A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 19, 2019
    Assignee: Japan Display Inc.
    Inventor: Satoshi Maruyama
  • Patent number: 10236365
    Abstract: A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same material—graphene.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 19, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Adam L. Friedman, Olaf M. J. van 't Erve, Jeremy T. Robinson, Berend T. Jonker, Keith E. Whitener
  • Patent number: 10229989
    Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Matsuura
  • Patent number: 10229903
    Abstract: In a semiconductor device including a resistance element, an electrostatic protection element, including a parasitic bipolar transistor having the resistance element as a component, is provided. That is, instead of providing a dedicated electrostatic protection element in a semiconductor device, a function as an electrostatic protection element is also achieved by using a resistance element provided in a semiconductor device.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Eisuke Kodama
  • Patent number: 10229929
    Abstract: Disclosed is a semiconductor memory device may include a substrate including a cell array region and a contact region and a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate. The stacking structure may include a stepwise structure in the contact region. Ones of the plurality of gate electrodes may include a respective pad unit that comprises a step of the stepwise structure. At least one of the pad units may include a base pad and a protrusion pad on the base pad. The protrusion pad may be between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Kim, Se Mee Jang
  • Patent number: 10229885
    Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Steffen Jordan
  • Patent number: 10224514
    Abstract: Disclosed herein is a transparent glass system that includes an optical grade silicon substrate, a transparent substrate layer; a titanium dioxide transparent layer, the transparent layer having an index of refraction of 2.35 or greater; and a polycrystalline diamond layer, wherein the transparent layer is between the substrate layer and the polycrystalline diamond layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 5, 2019
    Inventors: Adam Khan, Robert Polak, Priya Raman
  • Patent number: 10224505
    Abstract: A method for manufacturing a flexible organic light-emitting diode (OLED) panel and an OLED panel are provided. The method includes providing an organic material substrate, depositing a protective metal layer over the organic material substrate, depositing a buffer layer over the protective metal layer using a high temperature plasma enhanced chemical vapor deposition (PECVD) process, and forming a semiconductor layer over the buffer layer. The protective metal layer prevents a manufacturing process of the buffer layer from contaminating a PECVD cavity and pipe.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 5, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Pengzhen Zhang
  • Patent number: 10209688
    Abstract: A thermostat may include a plurality of heat-generating components; a plurality of first temperature sensors, each of the plurality of first temperature sensors being disposed next to a corresponding one of the plurality of heat-generating components; a second temperature sensor that is disposed away from the plurality of heat-generating components; and a memory device storing a coefficient matrix. The thermostat may also include one or more processors that combine a plurality of inputs to calculate an ambient temperature for an enclosure in which the thermostat is installed, the plurality of inputs including readings from the plurality of first temperature sensors, readings from the second temperature sensor, and the coefficient matrix.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 19, 2019
    Assignee: Google LLC
    Inventors: John Stefanski, Vivek Goyal, Orville Buenaventura, Alexander Schoenen, Mark Stefanski
  • Patent number: 10204321
    Abstract: The device for searching for similar breakdown cases according to the present invention includes: a first means that detects a signal abnormality from a repair target machine, calculates the correlations between the signal abnormality and past abnormality cases by means of quantification, and regards the past abnormality cases as similar abnormality cases; a second means that obtains the component repair histories of the repair target machine in the similar abnormality cases by means of quantification; and a third means that, in accordance with the quantified correlations and the quantified component repair histories, determines and provides the priority levels of the plural past similar abnormality cases.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uchida, Hideaki Suzuki, Junsuke Fujiwara, Shinya Yuda
  • Patent number: 10205030
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 10199396
    Abstract: A display device and a method of fabricating the display device may simplify a fabrication process and reduce fabrication cost. The display device includes: a substrate; a gate line and a data line on the substrate; a switching element connected to the gate line and the data line, the switching element including a source electrode and a drain electrode; and a first pixel electrode connected to the switching element. At least one of the source electrode and the drain electrode of the switching element includes substantially a same material as a material included in the first pixel electrode.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joonggun Chong, Yeogeon Yoon, Juae Youn, Jehong Choi
  • Patent number: 10199264
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Roderick A. Augur, Hoon Kim
  • Patent number: 10197702
    Abstract: Methods of forming a geologic map usable for identifying prospective resource accumulations beneath the earth-surface are disclosed herein. The methods include obtaining a seismic stratigraphic structure of a subsurface region of the earth, determining a plurality of potential resistivity boundaries from the seismic stratigraphic structure, obtaining an electromagnetic data set resulting from an electromagnetic data acquisition of the subsurface region, recovering a resistivity map of the subsurface region by performing an inversion process guided by the seismic information, and resolving a geologic map from the resistivity map.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 5, 2019
    Assignee: PGS GEOPHYSICAL AS
    Inventors: Zhijun Du, Md. Anwar Hossain Bhuiyan, Eivind Rødnes Vesterås, Allan John McKay