Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Abstract: In one example, a semiconductor device comprises a substrate having a top surface and a bottom surface, an electronic device on the bottom surface of the substrate, a leadframe on the bottom surface of the substrate, the leadframe comprising a paddle, wherein the paddle is coupled to the electronic device, and a lead electrically coupled to the electronic device. The semiconductor device further comprises a first protective material contacting the bottom surface of the substrate and a side surface of the electronic device.

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Abstract: A display device includes a first thin-film transistor (TFT) including a first semiconductor layer including silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode, a second TFT arranged on the first interlayer insulating layer and including a second semiconductor layer including oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a second interlayer insulating layer covering the second gate electrode, a first power supply voltage line arranged on the second interlayer insulating layer, a first planarization layer covering the first power supply voltage line, and a data line arranged on the first planarization layer and at least partially overlapping the first power supply voltage line.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.

Abstract: A display device includes first and second light emitting regions; first and second pixel electrodes in the first and second light emitting regions, respectively; a first organic layer in the first light emitting region, including first and second light emitting layers; a second organic layer in the second light emitting region, including a third light emitting layer; a common electrode on the first and second organic layers; a wavelength conversion pattern on the common electrode, overlapping the first organic layer, and wavelength-converting light of a first color into light of a second color, different from the first color; and a light transmitting pattern on the common electrode, overlapping the second organic layer. The third light emitting layer and one of the first and second light emitting layers emit light of the first color, and another one of the first and second light emitting layers emits light of the second color.

Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: A display apparatus can include a driving circuit on a device substrate, the driving circuit including a first thin film transistor and a second thin film transistor, a first insulating layer on the first thin film transistor and the second thin film transistor of the driving circuit, a second insulating layer on the first insulating layer, and a light-emitting device on the second insulating layer, the light-emitting device being electrically connected to the second thin film transistor of the driving circuit. Each of the first thin film transistor and the second thin film transistor includes an oxide semiconductor pattern and a gate electrode overlapping a portion of the oxide semiconductor pattern. The gate electrode has a stacked structure of a first hydrogen barrier layer and a low-resistance electrode.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: Disclosed are methods and systems for depositing layers comprising vanadium, nitrogen, and element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon. The layers are deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

Abstract: A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F2 and 4F2.

Abstract: Provided are a thin film transistor array substrate and an electronic device including the same. More specifically, the thin film transistor array includes a first active layer including a first area, a second area spaced apart from the first area, and a channel area provided between the first area and the second area, a first gate electrode disposed on the first active layer, and a second gate electrode disposed on the same layer as the first gate electrode to overlap one end of the first gate electrode and to which a signal corresponding to a signal applied to the first gate electrode is applied. Therefore, it is possible to have a structure for simultaneously controlling the threshold voltage, mobility, and subthreshold (S) parameter of a thin film transistor.

Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.